13d0407baSopenharmony_ci/* 23d0407baSopenharmony_ci * Copyright (c) 2022 FuZhou Lockzhiner Electronic Co., Ltd. All rights reserved. 33d0407baSopenharmony_ci * Licensed under the Apache License, Version 2.0 (the "License"); 43d0407baSopenharmony_ci * you may not use this file except in compliance with the License. 53d0407baSopenharmony_ci * You may obtain a copy of the License at 63d0407baSopenharmony_ci * 73d0407baSopenharmony_ci * http://www.apache.org/licenses/LICENSE-2.0 83d0407baSopenharmony_ci * 93d0407baSopenharmony_ci * Unless required by applicable law or agreed to in writing, software 103d0407baSopenharmony_ci * distributed under the License is distributed on an "AS IS" BASIS, 113d0407baSopenharmony_ci * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 123d0407baSopenharmony_ci * See the License for the specific language governing permissions and 133d0407baSopenharmony_ci * limitations under the License. 143d0407baSopenharmony_ci */ 153d0407baSopenharmony_ci 163d0407baSopenharmony_ci#ifndef _LINK_H 173d0407baSopenharmony_ci#define _LINK_H 183d0407baSopenharmony_ci 193d0407baSopenharmony_ci#ifdef __cplusplus 203d0407baSopenharmony_ci#if __cplusplus 213d0407baSopenharmony_ciextern "C" { 223d0407baSopenharmony_ci#endif /* __cplusplus */ 233d0407baSopenharmony_ci#endif /* __cplusplus */ 243d0407baSopenharmony_ci 253d0407baSopenharmony_ci#define PART_BLOCK_SIZE 0X200 // 512Byte 263d0407baSopenharmony_ci#define PART_SYSTEM_ADDR 0x00 273d0407baSopenharmony_ci#define PART_SYSTEM_BLOCKS 0x80 // 64K 283d0407baSopenharmony_ci#define PART_LOADER_ADDR (PART_SYSTEM_ADDR + PART_SYSTEM_BLOCKS * PART_BLOCK_SIZE) 293d0407baSopenharmony_ci#define PART_LOADER_BLOCKS 0x80 // 64K 303d0407baSopenharmony_ci#define PART_LITEOS_ADDR (PART_LOADER_ADDR + PART_LOADER_BLOCKS * PART_BLOCK_SIZE) 313d0407baSopenharmony_ci#define PART_LITEOS_BLOCKS 0x0F00 // (1M - 128K) 323d0407baSopenharmony_ci#define PART_ROOTFS_ADDR (PART_LITEOS_ADDR + PART_LITEOS_BLOCKS * PART_BLOCK_SIZE) 333d0407baSopenharmony_ci#define PART_ROOTFS_BLOCKS 0X2000 // 4M 343d0407baSopenharmony_ci#define PART_USERFS_ADDR (PART_ROOTFS_ADDR + PART_ROOTFS_BLOCKS * PART_BLOCK_SIZE) 353d0407baSopenharmony_ci#define PART_USERFS_BLOCKS 0x1000 // 2M 363d0407baSopenharmony_ci 373d0407baSopenharmony_ci#define FIRMWARE_VENDOR_OFFSET (PART_LITEOS_ADDR + 1 * PART_BLOCK_SIZE); 383d0407baSopenharmony_ci#define FIRMWARE_WIFI_OFFSET 0x20c00 393d0407baSopenharmony_ci#define FIRMWARE_WIFI_SIZE 0x40000 403d0407baSopenharmony_ci 413d0407baSopenharmony_ci/* if GRF_SOC_CON0.remap==1’b1, ICACHE access: 0X00080000 or 0x00000000 */ 423d0407baSopenharmony_ci#define SRAM0_ICACHE_ADDR 0x00080000 433d0407baSopenharmony_ci#define SRAM0_DCACHE_ADDR 0x20000000 443d0407baSopenharmony_ci#define SRAM0_SIZE 0x20000 // 128K 453d0407baSopenharmony_ci 463d0407baSopenharmony_ci#define SRAM1_ICACHE_ADDR 0x000A0000 473d0407baSopenharmony_ci#define SRAM1_DCACHE_ADDR 0x20020000 483d0407baSopenharmony_ci#define SRAM1_SIZE 0x20000 // 128K 493d0407baSopenharmony_ci 503d0407baSopenharmony_ci#define XIP_ADDR 0x10000000 513d0407baSopenharmony_ci#define XIP_SIZE 0x800000 // 8M 523d0407baSopenharmony_ci 533d0407baSopenharmony_ci#define SRAM_CODE_ADDR SRAM0_ICACHE_ADDR 543d0407baSopenharmony_ci#define SRAM_CODE_SIZE 0x26000 // 128K 553d0407baSopenharmony_ci 563d0407baSopenharmony_ci#define SRAM_DATA_ADDR (SRAM0_DCACHE_ADDR + SRAM_CODE_SIZE) 573d0407baSopenharmony_ci#define SRAM_DATA_SIZE (SRAM0_SIZE + SRAM1_SIZE - SRAM_CODE_SIZE) 583d0407baSopenharmony_ci 593d0407baSopenharmony_ci#define PSRAM_ADDR 0x38000000 603d0407baSopenharmony_ci#define PSRAM_SIZE 0x00800000 613d0407baSopenharmony_ci 623d0407baSopenharmony_ci#define SYS_STACK_SIZE 0x100000 633d0407baSopenharmony_ci 643d0407baSopenharmony_ci#ifdef __cplusplus 653d0407baSopenharmony_ci#if __cplusplus 663d0407baSopenharmony_ci} 673d0407baSopenharmony_ci#endif /* __cplusplus */ 683d0407baSopenharmony_ci#endif /* __cplusplus */ 693d0407baSopenharmony_ci 703d0407baSopenharmony_ci#endif /* _LINK_H */ 71