1/* 2 * Rockchip MIPI RX Synopsys/Innosilicon DPHY driver 3 * 4 * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd. 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenIB.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35#include <linux/clk.h> 36#include <linux/delay.h> 37#include <linux/io.h> 38#include <linux/module.h> 39#include <linux/of.h> 40#include <linux/of_graph.h> 41#include <linux/of_platform.h> 42#include <linux/platform_device.h> 43#include <linux/pm_runtime.h> 44#include <linux/regmap.h> 45#include <linux/mfd/syscon.h> 46#include <media/media-entity.h> 47#include <media/v4l2-ctrls.h> 48#include <media/v4l2-fwnode.h> 49#include <media/v4l2-subdev.h> 50#include <media/v4l2-device.h> 51 52/* GRF */ 53#define RK1808_GRF_PD_VI_CON_OFFSET 0x0430 54 55#define RK3288_GRF_SOC_CON6 0x025c 56#define RK3288_GRF_SOC_CON8 0x0264 57#define RK3288_GRF_SOC_CON9 0x0268 58#define RK3288_GRF_SOC_CON10 0x026c 59#define RK3288_GRF_SOC_CON14 0x027c 60#define RK3288_GRF_SOC_STATUS21 0x02d4 61#define RK3288_GRF_IO_VSEL 0x0380 62#define RK3288_GRF_SOC_CON15 0x03a4 63 64#define RK3326_GRF_IO_VSEL_OFFSET 0x0180 65#define RK3326_GRF_PD_VI_CON_OFFSET 0x0430 66 67#define RK3368_GRF_SOC_CON6_OFFSET 0x0418 68#define RK3368_GRF_IO_VSEL_OFFSET 0x0900 69 70#define RK3399_GRF_SOC_CON9 0x6224 71#define RK3399_GRF_SOC_CON21 0x6254 72#define RK3399_GRF_SOC_CON22 0x6258 73#define RK3399_GRF_SOC_CON23 0x625c 74#define RK3399_GRF_SOC_CON24 0x6260 75#define RK3399_GRF_SOC_CON25 0x6264 76#define RK3399_GRF_SOC_STATUS1 0xe2a4 77#define RK3399_GRF_IO_VSEL 0x0900 78 79#define RV1126_GRF_CSIPHY0_CON 0x10200 80#define RV1126_GRF_CSIPHY1_CON 0x10210 81#define RV1126_GRF_IOFUNC_CON3 0x1026c 82#define RV1126_GRF_PHY1_SEL_CIFLITE BIT(2) 83#define RV1126_GRF_PHY1_SEL_ISP BIT(1) 84#define RV1126_GRF_PHY1_SEL_CIF BIT(0) 85 86/* PHY */ 87#define RK3288_PHY_TEST_CTRL0 0x30 88#define RK3288_PHY_TEST_CTRL1 0x34 89#define RK3288_PHY_SHUTDOWNZ 0x08 90#define RK3288_PHY_RSTZ 0x0c 91 92#define RK3399_PHY_TEST_CTRL0 0xb4 93#define RK3399_PHY_TEST_CTRL1 0xb8 94#define RK3399_PHY_SHUTDOWNZ 0xa0 95#define RK3399_PHY_RSTZ 0xa0 96 97#define CLOCK_LANE_HS_RX_CONTROL 0x34 98#define LANE0_HS_RX_CONTROL 0x44 99#define LANE1_HS_RX_CONTROL 0x54 100#define LANE2_HS_RX_CONTROL 0x84 101#define LANE3_HS_RX_CONTROL 0x94 102#define HS_RX_DATA_LANES_THS_SETTLE_CONTROL 0x75 103 104/* LOW POWER MODE SET */ 105#define MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 0xFFFF 106 107#define RK1808_CSI_DPHY_CTRL_LANE_ENABLE 0x00 108#define RK1808_CSI_DPHY_CTRL_PWRCTL MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 109#define RK1808_CSI_DPHY_CTRL_DIG_RST 0x80 110 111#define RK3326_CSI_DPHY_CTRL_LANE_ENABLE 0x00 112#define RK3326_CSI_DPHY_CTRL_PWRCTL 0x04 113#define RK3326_CSI_DPHY_CTRL_DIG_RST 0x80 114 115#define RK3368_CSI_DPHY_CTRL_LANE_ENABLE 0x00 116#define RK3368_CSI_DPHY_CTRL_PWRCTL 0x04 117#define RK3368_CSI_DPHY_CTRL_DIG_RST 0x80 118 119#define RV1126_CSI_DPHY_CTRL_LANE_ENABLE 0x00 120#define RV1126_CSI_DPHY_CTRL_PWRCTL MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 121#define RV1126_CSI_DPHY_CTRL_DIG_RST 0x80 122 123#define MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT 2 124#define MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT 6 125 126/* Configure the count time of the THS-SETTLE by protocol. */ 127#define RK1808_CSI_DPHY_CLK_WR_THS_SETTLE 0x160 128#define RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE (RK1808_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80) 129#define RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE (RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80) 130#define RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE (RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80) 131#define RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE (RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80) 132 133#define RK3326_CSI_DPHY_CLK_WR_THS_SETTLE 0x100 134#define RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE (RK3326_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80) 135#define RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE (RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80) 136#define RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE (RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80) 137#define RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE (RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80) 138 139#define RK3368_CSI_DPHY_CLK_WR_THS_SETTLE 0x100 140#define RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE (RK3368_CSI_DPHY_CLK_WR_THS_SETTLE + 0x80) 141#define RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE (RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE + 0x80) 142#define RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE (RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE + 0x80) 143#define RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE (RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE + 0x80) 144 145#define RV1126_CSI_DPHY_CLK_WR_THS_SETTLE 0x160 146#define RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE 0x1e0 147#define RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE 0x260 148#define RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE 0x2e0 149#define RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE 0x360 150 151/* Calibration reception enable */ 152#define RK1808_CSI_DPHY_CLK_CALIB_EN 0x168 153#define RK1808_CSI_DPHY_LANE0_CALIB_EN 0x1e8 154#define RK1808_CSI_DPHY_LANE1_CALIB_EN 0x268 155#define RK1808_CSI_DPHY_LANE2_CALIB_EN 0x2e8 156#define RK1808_CSI_DPHY_LANE3_CALIB_EN 0x368 157 158#define RK3326_CSI_DPHY_CLK_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 159#define RK3326_CSI_DPHY_LANE0_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 160#define RK3326_CSI_DPHY_LANE1_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 161#define RK3326_CSI_DPHY_LANE2_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 162#define RK3326_CSI_DPHY_LANE3_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 163 164#define RK3368_CSI_DPHY_CLK_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 165#define RK3368_CSI_DPHY_LANE0_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 166#define RK3368_CSI_DPHY_LANE1_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 167#define RK3368_CSI_DPHY_LANE2_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 168#define RK3368_CSI_DPHY_LANE3_CALIB_EN MIPI_CSI_DPHY_CTRL_INVALID_OFFSET 169 170#define RV1126_CSI_DPHY_CLK_CALIB_EN 0x168 171#define RV1126_CSI_DPHY_LANE0_CALIB_EN 0x1e8 172#define RV1126_CSI_DPHY_LANE1_CALIB_EN 0x268 173#define RV1126_CSI_DPHY_LANE2_CALIB_EN 0x2e8 174#define RV1126_CSI_DPHY_LANE3_CALIB_EN 0x368 175 176#define RV1126_CSI_DPHY_MIPI_LVDS_MODEL 0x2cc 177#define RV1126_CSI_DPHY_LVDS_MODE 0x300 178/* 179 * CSI HOST 180 */ 181#define PHY_TESTEN_ADDR (0x1 << 16) 182#define PHY_TESTEN_DATA (0x0 << 16) 183#define PHY_TESTCLK (0x1 << 1) 184#define PHY_TESTCLR (0x1 << 0) 185#define THS_SETTLE_COUNTER_THRESHOLD 0x04 186 187#define HIWORD_UPDATE(val, mask, shift) ((val) << (shift) | (mask) << ((shift) + 16)) 188 189enum mipi_dphy_chip_id { 190 CHIP_ID_RK1808 = 0, 191 CHIP_ID_RK3288, 192 CHIP_ID_RK3326, 193 CHIP_ID_RK3368, 194 CHIP_ID_RK3399, 195 CHIP_ID_RK1126, 196}; 197 198enum mipi_dphy_rx_pads { 199 MIPI_DPHY_RX_PAD_SINK = 0, 200 MIPI_DPHY_RX_PAD_SOURCE, 201 MIPI_DPHY_RX_PADS_NUM, 202}; 203 204enum dphy_reg_id { 205 GRF_DPHY_RX0_TURNDISABLE = 0, 206 GRF_DPHY_RX0_FORCERXMODE, 207 GRF_DPHY_RX0_FORCETXSTOPMODE, 208 GRF_DPHY_RX0_ENABLE, 209 GRF_DPHY_RX0_TESTCLR, 210 GRF_DPHY_RX0_TESTCLK, 211 GRF_DPHY_RX0_TESTEN, 212 GRF_DPHY_RX0_TESTDIN, 213 GRF_DPHY_RX0_TURNREQUEST, 214 GRF_DPHY_RX0_TESTDOUT, 215 GRF_DPHY_TX0_TURNDISABLE, 216 GRF_DPHY_TX0_FORCERXMODE, 217 GRF_DPHY_TX0_FORCETXSTOPMODE, 218 GRF_DPHY_TX0_TURNREQUEST, 219 GRF_DPHY_TX1RX1_TURNDISABLE, 220 GRF_DPHY_TX1RX1_FORCERXMODE, 221 GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 222 GRF_DPHY_TX1RX1_ENABLE, 223 GRF_DPHY_TX1RX1_MASTERSLAVEZ, 224 GRF_DPHY_TX1RX1_BASEDIR, 225 GRF_DPHY_TX1RX1_ENABLECLK, 226 GRF_DPHY_TX1RX1_TURNREQUEST, 227 GRF_DPHY_RX1_SRC_SEL, 228 /* rk3288 only */ 229 GRF_CON_DISABLE_ISP, 230 GRF_CON_ISP_DPHY_SEL, 231 GRF_DSI_CSI_TESTBUS_SEL, 232 GRF_DVP_V18SEL, 233 /* rk1808 & rk3326 & rv1126 */ 234 GRF_DPHY_CSIPHY_FORCERXMODE, 235 GRF_DPHY_CSIPHY_CLKLANE_EN, 236 GRF_DPHY_CSIPHY_DATALANE_EN, 237 /* rv1126 only */ 238 GRF_DPHY_CLK_INV_SEL, 239 GRF_DPHY_SEL, 240 /* rk3368 only */ 241 GRF_ISP_MIPI_CSI_HOST_SEL, 242 /* below is for rk3399 only */ 243 GRF_DPHY_RX0_CLK_INV_SEL, 244 GRF_DPHY_RX1_CLK_INV_SEL, 245 GRF_DPHY_TX1RX1_SRC_SEL, 246}; 247 248enum csiphy_reg_id { 249 CSIPHY_CTRL_LANE_ENABLE = 0, 250 CSIPHY_CTRL_PWRCTL, 251 CSIPHY_CTRL_DIG_RST, 252 CSIPHY_CLK_THS_SETTLE, 253 CSIPHY_LANE0_THS_SETTLE, 254 CSIPHY_LANE1_THS_SETTLE, 255 CSIPHY_LANE2_THS_SETTLE, 256 CSIPHY_LANE3_THS_SETTLE, 257 CSIPHY_CLK_CALIB_ENABLE, 258 CSIPHY_LANE0_CALIB_ENABLE, 259 CSIPHY_LANE1_CALIB_ENABLE, 260 CSIPHY_LANE2_CALIB_ENABLE, 261 CSIPHY_LANE3_CALIB_ENABLE, 262 // rv1126 only 263 CSIPHY_MIPI_LVDS_MODEL, 264 CSIPHY_LVDS_MODE, 265}; 266 267enum mipi_dphy_ctl_type { MIPI_DPHY_CTL_GRF_ONLY = 0, MIPI_DPHY_CTL_CSI_HOST }; 268 269enum mipi_dphy_lane { 270 MIPI_DPHY_LANE_CLOCK = 0, 271 MIPI_DPHY_LANE_DATA0, 272 MIPI_DPHY_LANE_DATA1, 273 MIPI_DPHY_LANE_DATA2, 274 MIPI_DPHY_LANE_DATA3 275}; 276 277enum txrx_reg_id { 278 TXRX_PHY_TEST_CTRL0 = 0, 279 TXRX_PHY_TEST_CTRL1, 280 TXRX_PHY_SHUTDOWNZ, 281 TXRX_PHY_RSTZ, 282}; 283 284struct dphy_reg { 285 u32 offset; 286 u32 mask; 287 u32 shift; 288}; 289 290struct txrx_reg { 291 u32 offset; 292}; 293 294struct csiphy_reg { 295 u32 offset; 296}; 297 298#define PHY_REG(_offset, _width, _shift) \ 299 { \ 300 .offset = (_offset), .mask = BIT(_width) - 1, .shift = (_shift), \ 301 } 302 303#define TXRX_REG(_offset) \ 304 { \ 305 .offset = (_offset), \ 306 } 307 308#define CSIPHY_REG(_offset) \ 309 { \ 310 .offset = (_offset), \ 311 } 312 313static const struct dphy_reg rk1808_grf_dphy_regs[] = { 314 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 0), 315 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 1, 8), 316 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK1808_GRF_PD_VI_CON_OFFSET, 4, 4), 317}; 318 319static const struct dphy_reg rk3288_grf_dphy_regs[] = { 320 [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0), 321 [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1), 322 [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14), 323 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0), 324 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4), 325 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8), 326 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0), 327 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4), 328 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8), 329 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12), 330 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0), 331 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4), 332 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8), 333 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12), 334 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0), 335 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1), 336 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2), 337 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3), 338 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12), 339 [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13), 340 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14), 341 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15), 342 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0), 343 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4), 344 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8), 345 [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1), 346 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0), 347}; 348 349static const struct dphy_reg rk3326_grf_dphy_regs[] = { 350 [GRF_DVP_V18SEL] = PHY_REG(RK3326_GRF_IO_VSEL_OFFSET, 1, 4), 351 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 0), 352 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 1, 8), 353 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RK3326_GRF_PD_VI_CON_OFFSET, 4, 4), 354}; 355 356static const struct dphy_reg rk3368_grf_dphy_regs[] = { 357 [GRF_DVP_V18SEL] = PHY_REG(RK3368_GRF_IO_VSEL_OFFSET, 1, 1), 358 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 4, 8), 359 [GRF_ISP_MIPI_CSI_HOST_SEL] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 1), 360 [GRF_CON_DISABLE_ISP] = PHY_REG(RK3368_GRF_SOC_CON6_OFFSET, 1, 0), 361}; 362 363static const struct dphy_reg rk3399_grf_dphy_regs[] = { 364 [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0), 365 [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10), 366 [GRF_DPHY_RX1_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 11), 367 [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 0), 368 [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 4), 369 [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 8), 370 [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON21, 4, 12), 371 [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 0), 372 [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 4), 373 [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 8), 374 [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON22, 4, 12), 375 [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 0), 376 [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 4), 377 [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 8), 378 [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3399_GRF_SOC_CON23, 4, 12), 379 [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON24, 4, 0), 380 [GRF_DPHY_TX1RX1_SRC_SEL] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 4), 381 [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 5), 382 [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 6), 383 [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3399_GRF_SOC_CON24, 1, 7), 384 [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3399_GRF_SOC_CON25, 8, 0), 385 [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 8), 386 [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 9), 387 [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3399_GRF_SOC_CON25, 1, 10), 388 [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3399_GRF_SOC_STATUS1, 8, 0), 389 [GRF_DVP_V18SEL] = PHY_REG(RK3399_GRF_IO_VSEL, 1, 1), 390}; 391 392static const struct dphy_reg rv1126_grf_dphy0_regs[] = { 393 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 0), 394 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 4, 4), 395 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 8), 396 [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY0_CON, 1, 9), 397 [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9), 398}; 399 400static const struct dphy_reg rv1126_grf_dphy1_regs[] = { 401 [GRF_DPHY_CSIPHY_FORCERXMODE] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 0), 402 [GRF_DPHY_CSIPHY_DATALANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 4, 4), 403 [GRF_DPHY_CSIPHY_CLKLANE_EN] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 8), 404 [GRF_DPHY_CLK_INV_SEL] = PHY_REG(RV1126_GRF_CSIPHY1_CON, 1, 9), 405 [GRF_DPHY_SEL] = PHY_REG(RV1126_GRF_IOFUNC_CON3, 3, 9), 406}; 407 408static const struct txrx_reg rk3288_txrx_regs[] = { 409 [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3288_PHY_TEST_CTRL0), 410 [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3288_PHY_TEST_CTRL1), 411 [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3288_PHY_SHUTDOWNZ), 412 [TXRX_PHY_RSTZ] = TXRX_REG(RK3288_PHY_RSTZ), 413}; 414 415static const struct txrx_reg rk3399_txrx_regs[] = { 416 [TXRX_PHY_TEST_CTRL0] = TXRX_REG(RK3399_PHY_TEST_CTRL0), 417 [TXRX_PHY_TEST_CTRL1] = TXRX_REG(RK3399_PHY_TEST_CTRL1), 418 [TXRX_PHY_SHUTDOWNZ] = TXRX_REG(RK3399_PHY_SHUTDOWNZ), 419 [TXRX_PHY_RSTZ] = TXRX_REG(RK3399_PHY_RSTZ), 420}; 421 422static const struct csiphy_reg rk1808_csiphy_regs[] = { 423 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_LANE_ENABLE), 424 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_PWRCTL), 425 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK1808_CSI_DPHY_CTRL_DIG_RST), 426 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_WR_THS_SETTLE), 427 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_WR_THS_SETTLE), 428 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_WR_THS_SETTLE), 429 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_WR_THS_SETTLE), 430 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_WR_THS_SETTLE), 431 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_CLK_CALIB_EN), 432 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE0_CALIB_EN), 433 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE1_CALIB_EN), 434 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE2_CALIB_EN), 435 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK1808_CSI_DPHY_LANE3_CALIB_EN), 436}; 437 438static const struct csiphy_reg rk3326_csiphy_regs[] = { 439 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_LANE_ENABLE), 440 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_PWRCTL), 441 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3326_CSI_DPHY_CTRL_DIG_RST), 442 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_WR_THS_SETTLE), 443 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_WR_THS_SETTLE), 444 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_WR_THS_SETTLE), 445 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_WR_THS_SETTLE), 446 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_WR_THS_SETTLE), 447 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_CLK_CALIB_EN), 448 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE0_CALIB_EN), 449 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE1_CALIB_EN), 450 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE2_CALIB_EN), 451 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3326_CSI_DPHY_LANE3_CALIB_EN), 452}; 453 454static const struct csiphy_reg rk3368_csiphy_regs[] = { 455 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_LANE_ENABLE), 456 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_PWRCTL), 457 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RK3368_CSI_DPHY_CTRL_DIG_RST), 458 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_WR_THS_SETTLE), 459 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_WR_THS_SETTLE), 460 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_WR_THS_SETTLE), 461 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_WR_THS_SETTLE), 462 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_WR_THS_SETTLE), 463 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_CLK_CALIB_EN), 464 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE0_CALIB_EN), 465 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE1_CALIB_EN), 466 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE2_CALIB_EN), 467 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RK3368_CSI_DPHY_LANE3_CALIB_EN), 468}; 469 470static const struct csiphy_reg rv1126_csiphy_regs[] = { 471 [CSIPHY_CTRL_LANE_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_LANE_ENABLE), 472 [CSIPHY_CTRL_PWRCTL] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_PWRCTL), 473 [CSIPHY_CTRL_DIG_RST] = CSIPHY_REG(RV1126_CSI_DPHY_CTRL_DIG_RST), 474 [CSIPHY_CLK_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_WR_THS_SETTLE), 475 [CSIPHY_LANE0_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_WR_THS_SETTLE), 476 [CSIPHY_LANE1_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_WR_THS_SETTLE), 477 [CSIPHY_LANE2_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_WR_THS_SETTLE), 478 [CSIPHY_LANE3_THS_SETTLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_WR_THS_SETTLE), 479 [CSIPHY_CLK_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_CLK_CALIB_EN), 480 [CSIPHY_LANE0_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE0_CALIB_EN), 481 [CSIPHY_LANE1_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE1_CALIB_EN), 482 [CSIPHY_LANE2_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE2_CALIB_EN), 483 [CSIPHY_LANE3_CALIB_ENABLE] = CSIPHY_REG(RV1126_CSI_DPHY_LANE3_CALIB_EN), 484 [CSIPHY_MIPI_LVDS_MODEL] = CSIPHY_REG(RV1126_CSI_DPHY_MIPI_LVDS_MODEL), 485 [CSIPHY_LVDS_MODE] = CSIPHY_REG(RV1126_CSI_DPHY_LVDS_MODE), 486}; 487 488struct hsfreq_range { 489 u32 range_h; 490 u8 cfg_bit; 491}; 492 493struct mipidphy_priv; 494 495struct dphy_drv_data { 496 const char *const *clks; 497 int num_clks; 498 const struct hsfreq_range *hsfreq_ranges; 499 int num_hsfreq_ranges; 500 const struct dphy_reg *grf_regs; 501 const struct txrx_reg *txrx_regs; 502 const struct csiphy_reg *csiphy_regs; 503 enum mipi_dphy_ctl_type ctl_type; 504 void (*individual_init)(struct mipidphy_priv *priv); 505 enum mipi_dphy_chip_id chip_id; 506}; 507 508struct sensor_async_subdev { 509 struct v4l2_async_subdev asd; 510 struct v4l2_mbus_config mbus; 511 int lanes; 512}; 513 514#define MAX_DPHY_CLK 8 515#define MAX_DPHY_SENSORS 2 516 517struct mipidphy_sensor { 518 struct v4l2_subdev *sd; 519 struct v4l2_mbus_config mbus; 520 struct v4l2_mbus_framefmt format; 521 int lanes; 522}; 523 524struct mipidphy_priv { 525 struct device *dev; 526 struct regmap *regmap_grf; 527 const struct dphy_reg *grf_regs; 528 const struct txrx_reg *txrx_regs; 529 const struct csiphy_reg *csiphy_regs; 530 void __iomem *csihost_base_addr; 531 struct clk *clks[MAX_DPHY_CLK]; 532 const struct dphy_drv_data *drv_data; 533 u64 data_rate_mbps; 534 struct v4l2_async_notifier notifier; 535 struct v4l2_subdev sd; 536 struct mutex mutex; /* lock for updating protection */ 537 struct media_pad pads[MIPI_DPHY_RX_PADS_NUM]; 538 struct mipidphy_sensor sensors[MAX_DPHY_SENSORS]; 539 int num_sensors; 540 int phy_index; 541 bool is_streaming; 542 void __iomem *txrx_base_addr; 543 int (*stream_on)(struct mipidphy_priv *priv, struct v4l2_subdev *sd); 544 int (*stream_off)(struct mipidphy_priv *priv, struct v4l2_subdev *sd); 545}; 546 547static inline struct mipidphy_priv *to_dphy_priv(struct v4l2_subdev *subdev) 548{ 549 return container_of(subdev, struct mipidphy_priv, sd); 550} 551 552static inline void write_grf_reg(struct mipidphy_priv *priv, int index, u8 value) 553{ 554 const struct dphy_reg *reg = &priv->grf_regs[index]; 555 unsigned int val = HIWORD_UPDATE(value, reg->mask, reg->shift); 556 557 if (reg->offset) { 558 regmap_write(priv->regmap_grf, reg->offset, val); 559 } 560} 561 562static inline u32 read_grf_reg(struct mipidphy_priv *priv, int index) 563{ 564 const struct dphy_reg *reg = &priv->grf_regs[index]; 565 unsigned int val = 0; 566 567 if (reg->offset) { 568 regmap_read(priv->regmap_grf, reg->offset, &val); 569 val = (val >> reg->shift) & reg->mask; 570 } 571 return val; 572} 573 574static inline void write_txrx_reg(struct mipidphy_priv *priv, int index, u32 value) 575{ 576 const struct txrx_reg *reg = &priv->txrx_regs[index]; 577 578 if (reg->offset) { 579 writel(value, priv->txrx_base_addr + reg->offset); 580 } 581} 582 583static void mipidphy0_wr_reg(struct mipidphy_priv *priv, u8 test_code, u8 test_data) 584{ 585 /* 586 * With the falling edge on TESTCLK, the TESTDIN[7:0] signal content 587 * is latched internally as the current test code. Test data is 588 * programmed internally by rising edge on TESTCLK. 589 */ 590 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1); 591 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_code); 592 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 1); 593 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 0); 594 write_grf_reg(priv, GRF_DPHY_RX0_TESTEN, 0); 595 write_grf_reg(priv, GRF_DPHY_RX0_TESTDIN, test_data); 596 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1); 597} 598 599static void mipidphy1_wr_reg(struct mipidphy_priv *priv, unsigned char addr, unsigned char data) 600{ 601 /* 602 * TESTEN =1,TESTDIN=addr 603 * TESTCLK=0 604 * TESTEN =0,TESTDIN=data 605 * TESTCLK=1 606 */ 607 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_ADDR | addr); 608 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x00); 609 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL1, PHY_TESTEN_DATA | data); 610 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, 0x02); 611} 612 613static inline void write_csiphy_reg(struct mipidphy_priv *priv, int index, u32 value) 614{ 615 const struct csiphy_reg *reg = &priv->csiphy_regs[index]; 616 617 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET) { 618 writel(value, priv->csihost_base_addr + reg->offset); 619 } 620} 621 622static inline void read_csiphy_reg(struct mipidphy_priv *priv, int index, u32 *value) 623{ 624 const struct csiphy_reg *reg = &priv->csiphy_regs[index]; 625 626 if (reg->offset != MIPI_CSI_DPHY_CTRL_INVALID_OFFSET) { 627 *value = readl(priv->csihost_base_addr + reg->offset); 628 } 629} 630 631static void csi_mipidphy_wr_ths_settle(struct mipidphy_priv *priv, int hsfreq, enum mipi_dphy_lane lane) 632{ 633 unsigned int val = 0; 634 unsigned int offset; 635 636 switch (lane) { 637 case MIPI_DPHY_LANE_CLOCK: 638 offset = CSIPHY_CLK_THS_SETTLE; 639 break; 640 case MIPI_DPHY_LANE_DATA0: 641 offset = CSIPHY_LANE0_THS_SETTLE; 642 break; 643 case MIPI_DPHY_LANE_DATA1: 644 offset = CSIPHY_LANE1_THS_SETTLE; 645 break; 646 case MIPI_DPHY_LANE_DATA2: 647 offset = CSIPHY_LANE2_THS_SETTLE; 648 break; 649 case MIPI_DPHY_LANE_DATA3: 650 offset = CSIPHY_LANE3_THS_SETTLE; 651 break; 652 default: 653 return; 654 } 655 656 read_csiphy_reg(priv, offset, &val); 657 val = (val & ~0x7f) | hsfreq; 658 write_csiphy_reg(priv, offset, val); 659} 660 661static struct v4l2_subdev *get_remote_sensor(struct v4l2_subdev *sd) 662{ 663 struct media_pad *local, *remote; 664 struct media_entity *sensor_me; 665 666 local = &sd->entity.pads[MIPI_DPHY_RX_PAD_SINK]; 667 remote = media_entity_remote_pad(local); 668 if (!remote) { 669 v4l2_warn(sd, "No link between dphy and sensor\n"); 670 return NULL; 671 } 672 673 sensor_me = media_entity_remote_pad(local)->entity; 674 return media_entity_to_v4l2_subdev(sensor_me); 675} 676 677static struct mipidphy_sensor *sd_to_sensor(struct mipidphy_priv *priv, struct v4l2_subdev *sd) 678{ 679 int i; 680 681 for (i = 0; i < priv->num_sensors; ++i) { 682 if (priv->sensors[i].sd == sd) { 683 return &priv->sensors[i]; 684 } 685 } 686 687 return NULL; 688} 689 690static int mipidphy_get_sensor_data_rate(struct v4l2_subdev *sd) 691{ 692 struct mipidphy_priv *priv = to_dphy_priv(sd); 693 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd); 694 struct v4l2_ctrl *link_freq; 695 struct v4l2_querymenu qm = { 696 .id = V4L2_CID_LINK_FREQ, 697 }; 698 int ret; 699 700 link_freq = v4l2_ctrl_find(sensor_sd->ctrl_handler, V4L2_CID_LINK_FREQ); 701 if (!link_freq) { 702 v4l2_warn(sd, "No pixel rate control in subdev\n"); 703 return -EPIPE; 704 } 705 706 qm.index = v4l2_ctrl_g_ctrl(link_freq); 707 ret = v4l2_querymenu(sensor_sd->ctrl_handler, &qm); 708 if (ret < 0) { 709 v4l2_err(sd, "Failed to get menu item\n"); 710 return ret; 711 } 712 713 if (!qm.value) { 714 v4l2_err(sd, "Invalid link_freq\n"); 715 return -EINVAL; 716 } 717 priv->data_rate_mbps = qm.value * 0x02; 718 do_div(priv->data_rate_mbps, 0x3E8 * 0x3E8); 719 v4l2_info(sd, "data_rate_mbps %lld\n", priv->data_rate_mbps); 720 return 0; 721} 722 723static int mipidphy_update_sensor_mbus(struct v4l2_subdev *sd) 724{ 725 struct mipidphy_priv *priv = to_dphy_priv(sd); 726 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd); 727 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd); 728 struct v4l2_mbus_config mbus; 729 int ret; 730 731 ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, &mbus); 732 if (ret) { 733 return ret; 734 } 735 736 sensor->mbus = mbus; 737 switch (mbus.flags & V4L2_MBUS_CSI2_LANES) { 738 case V4L2_MBUS_CSI2_1_LANE: 739 sensor->lanes = 1; 740 break; 741 case V4L2_MBUS_CSI2_2_LANE: 742 sensor->lanes = 0x02; 743 break; 744 case V4L2_MBUS_CSI2_3_LANE: 745 sensor->lanes = 0x03; 746 break; 747 case V4L2_MBUS_CSI2_4_LANE: 748 sensor->lanes = 0x04; 749 break; 750 default: 751 return -EINVAL; 752 } 753 754 return 0; 755} 756 757static void rk1126_mipidphy_dphy_sel(struct v4l2_subdev *sd) 758{ 759 struct mipidphy_priv *priv = to_dphy_priv(sd); 760 char *model; 761 u8 oldval, newval; 762 763 model = sd->v4l2_dev->mdev->model; 764 oldval = read_grf_reg(priv, GRF_DPHY_SEL); 765 newval = oldval; 766 if (!strncmp(model, "rkcif_lite_mipi_lvds", sizeof("rkcif_lite_mipi_lvds") - 1)) { 767 if (priv->phy_index == 0) { 768 newval &= ~RV1126_GRF_PHY1_SEL_CIFLITE; 769 } else { 770 newval |= RV1126_GRF_PHY1_SEL_CIFLITE; 771 } 772 } else if (!strncmp(model, "rkcif_mipi_lvds", sizeof("rkcif_mipi_lvds") - 1)) { 773 if (priv->phy_index == 0) { 774 newval &= ~RV1126_GRF_PHY1_SEL_CIF; 775 } else { 776 newval |= RV1126_GRF_PHY1_SEL_CIF; 777 } 778 } else { 779 if (priv->phy_index == 0) { 780 newval &= ~RV1126_GRF_PHY1_SEL_ISP; 781 } else { 782 newval |= RV1126_GRF_PHY1_SEL_ISP; 783 } 784 } 785 786 if (newval != oldval) { 787 write_grf_reg(priv, GRF_DPHY_SEL, newval); 788 } 789} 790 791static int mipidphy_s_stream_start(struct v4l2_subdev *sd) 792{ 793 struct mipidphy_priv *priv = to_dphy_priv(sd); 794 int ret = 0; 795 796 if (priv->is_streaming) { 797 return 0; 798 } 799 800 ret = mipidphy_get_sensor_data_rate(sd); 801 if (ret < 0) { 802 return ret; 803 } 804 805 if (priv->drv_data->chip_id == CHIP_ID_RK1126) { 806 rk1126_mipidphy_dphy_sel(sd); 807 } 808 809 mipidphy_update_sensor_mbus(sd); 810 priv->stream_on(priv, sd); 811 812 priv->is_streaming = true; 813 814 return 0; 815} 816 817static int mipidphy_s_stream_stop(struct v4l2_subdev *sd) 818{ 819 struct mipidphy_priv *priv = to_dphy_priv(sd); 820 821 if (!priv->is_streaming) { 822 return 0; 823 } 824 825 if (priv->stream_off) { 826 priv->stream_off(priv, sd); 827 } 828 priv->is_streaming = false; 829 830 return 0; 831} 832 833static int mipidphy_s_stream(struct v4l2_subdev *sd, int on) 834{ 835 int ret = 0; 836 struct mipidphy_priv *priv = to_dphy_priv(sd); 837 838 dev_info(priv->dev, "stream on:%d\n", on); 839 mutex_lock(&priv->mutex); 840 if (on) { 841 ret = mipidphy_s_stream_start(sd); 842 } else { 843 ret = mipidphy_s_stream_stop(sd); 844 } 845 mutex_unlock(&priv->mutex); 846 return ret; 847} 848 849static int mipidphy_g_frame_interval(struct v4l2_subdev *sd, struct v4l2_subdev_frame_interval *fi) 850{ 851 struct v4l2_subdev *sensor = get_remote_sensor(sd); 852 853 if (sensor) { 854 return v4l2_subdev_call(sensor, video, g_frame_interval, fi); 855 } 856 857 return -EINVAL; 858} 859 860static int mipidphy_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id, struct v4l2_mbus_config *config) 861{ 862 struct mipidphy_priv *priv = to_dphy_priv(sd); 863 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd); 864 struct mipidphy_sensor *sensor; 865 866 if (!sensor_sd) { 867 return -ENODEV; 868 } 869 sensor = sd_to_sensor(priv, sensor_sd); 870 mipidphy_update_sensor_mbus(sd); 871 *config = sensor->mbus; 872 873 return 0; 874} 875 876static int mipidphy_s_power(struct v4l2_subdev *sd, int on) 877{ 878 struct mipidphy_priv *priv = to_dphy_priv(sd); 879 880 if (on) { 881 return pm_runtime_get_sync(priv->dev); 882 } else { 883 return pm_runtime_put(priv->dev); 884 } 885} 886 887static int mipidphy_runtime_suspend(struct device *dev) 888{ 889 struct media_entity *me = dev_get_drvdata(dev); 890 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me); 891 struct mipidphy_priv *priv = to_dphy_priv(sd); 892 int i, num_clks; 893 894 num_clks = priv->drv_data->num_clks; 895 for (i = num_clks - 1; i >= 0; i--) { 896 if (!IS_ERR(priv->clks[i])) { 897 clk_disable_unprepare(priv->clks[i]); 898 } 899 } 900 901 return 0; 902} 903 904static int mipidphy_runtime_resume(struct device *dev) 905{ 906 struct media_entity *me = dev_get_drvdata(dev); 907 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me); 908 struct mipidphy_priv *priv = to_dphy_priv(sd); 909 int i, num_clks, ret; 910 911 num_clks = priv->drv_data->num_clks; 912 for (i = 0; i < num_clks; i++) { 913 if (!IS_ERR(priv->clks[i])) { 914 ret = clk_prepare_enable(priv->clks[i]); 915 if (ret < 0) { 916 goto err; 917 } 918 } 919 } 920 921 return 0; 922err: 923 while (--i >= 0) { 924 clk_disable_unprepare(priv->clks[i]); 925 } 926 return ret; 927} 928 929/* dphy accepts all fmt/size from sensor */ 930static int mipidphy_get_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, 931 struct v4l2_subdev_format *fmt) 932{ 933 struct mipidphy_priv *priv = to_dphy_priv(sd); 934 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd); 935 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd); 936 int ret; 937 /* 938 * Do not allow format changes and just relay whatever 939 * set currently in the sensor. 940 */ 941 if (!sensor_sd) { 942 return -ENODEV; 943 } 944 ret = v4l2_subdev_call(sensor_sd, pad, get_fmt, NULL, fmt); 945 if (!ret && fmt->pad == 0) { 946 sensor->format = fmt->format; 947 } 948 return ret; 949} 950 951static int mipidphy_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, 952 struct v4l2_subdev_selection *sel) 953{ 954 struct v4l2_subdev *sensor = get_remote_sensor(sd); 955 956 return v4l2_subdev_call(sensor, pad, get_selection, NULL, sel); 957} 958 959static const struct v4l2_subdev_pad_ops mipidphy_subdev_pad_ops = { 960 .set_fmt = mipidphy_get_set_fmt, 961 .get_fmt = mipidphy_get_set_fmt, 962 .get_selection = mipidphy_get_selection, 963 .get_mbus_config = mipidphy_g_mbus_config, 964}; 965 966static const struct v4l2_subdev_core_ops mipidphy_core_ops = { 967 .s_power = mipidphy_s_power, 968}; 969 970static const struct v4l2_subdev_video_ops mipidphy_video_ops = { 971 .g_frame_interval = mipidphy_g_frame_interval, 972 .s_stream = mipidphy_s_stream, 973}; 974 975static const struct v4l2_subdev_ops mipidphy_subdev_ops = { 976 .core = &mipidphy_core_ops, 977 .video = &mipidphy_video_ops, 978 .pad = &mipidphy_subdev_pad_ops, 979}; 980 981/* These tables must be sorted by .range_h ascending. */ 982static const struct hsfreq_range rk1808_rv1126_mipidphy_hsfreq_ranges[] = { 983 {109, 0x02}, {149, 0x03}, {199, 0x06}, {249, 0x06}, {299, 0x06}, {399, 0x08}, {499, 0x0b}, 984 {599, 0x0e}, {699, 0x10}, {799, 0x12}, {999, 0x16}, {1199, 0x1e}, {1399, 0x23}, {1599, 0x2d}, 985 {1799, 0x32}, {1999, 0x37}, {2199, 0x3c}, {2399, 0x41}, {2499, 0x46}}; 986 987static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = { 988 {89, 0x00}, {99, 0x10}, {109, 0x20}, {129, 0x01}, {139, 0x11}, {149, 0x21}, {169, 0x02}, {179, 0x12}, 989 {199, 0x22}, {219, 0x03}, {239, 0x13}, {249, 0x23}, {269, 0x04}, {299, 0x14}, {329, 0x05}, {359, 0x15}, 990 {399, 0x25}, {449, 0x06}, {499, 0x16}, {549, 0x07}, {599, 0x17}, {649, 0x08}, {699, 0x18}, {749, 0x09}, 991 {799, 0x19}, {849, 0x29}, {899, 0x39}, {949, 0x0a}, {999, 0x1a}}; 992 993static const struct hsfreq_range rk3326_mipidphy_hsfreq_ranges[] = { 994 {109, 0x00}, {149, 0x01}, {199, 0x02}, {249, 0x03}, {299, 0x04}, {399, 0x05}, {499, 0x06}, {599, 0x07}, 995 {699, 0x08}, {799, 0x09}, {899, 0x0a}, {1099, 0x0b}, {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}}; 996 997static const struct hsfreq_range rk3368_mipidphy_hsfreq_ranges[] = { 998 {109, 0x00}, {149, 0x01}, {199, 0x02}, {249, 0x03}, {299, 0x04}, {399, 0x05}, {499, 0x06}, {599, 0x07}, 999 {699, 0x08}, {799, 0x09}, {899, 0x0a}, {1099, 0x0b}, {1249, 0x0c}, {1349, 0x0d}, {1500, 0x0e}}; 1000 1001static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { 1002 {89, 0x00}, {99, 0x10}, {109, 0x20}, {129, 0x01}, {139, 0x11}, {149, 0x21}, {169, 0x02}, {179, 0x12}, 1003 {199, 0x22}, {219, 0x03}, {239, 0x13}, {249, 0x23}, {269, 0x04}, {299, 0x14}, {329, 0x05}, {359, 0x15}, 1004 {399, 0x25}, {449, 0x06}, {499, 0x16}, {549, 0x07}, {599, 0x17}, {649, 0x08}, {699, 0x18}, {749, 0x09}, 1005 {799, 0x19}, {849, 0x29}, {899, 0x39}, {949, 0x0a}, {999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b}, 1006 {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c}, {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c}}; 1007 1008static const char *const rk1808_mipidphy_clks[] = { 1009 "pclk", 1010}; 1011 1012static const char *const rk3288_mipidphy_clks[] = { 1013 "dphy-ref", 1014 "pclk", 1015}; 1016 1017static const char *const rk3326_mipidphy_clks[] = { 1018 "dphy-ref", 1019}; 1020 1021static const char *const rk3368_mipidphy_clks[] = { 1022 "pclk_dphyrx", 1023}; 1024 1025static const char *const rk3399_mipidphy_clks[] = { 1026 "dphy-ref", 1027 "dphy-cfg", 1028 "grf", 1029 "pclk_mipi_dsi", 1030}; 1031 1032static const char *const rv1126_mipidphy_clks[] = { 1033 "pclk", 1034}; 1035 1036static void default_mipidphy_individual_init(struct mipidphy_priv *priv) 1037{ 1038} 1039 1040static void rk3368_mipidphy_individual_init(struct mipidphy_priv *priv) 1041{ 1042 /* isp select */ 1043 write_grf_reg(priv, GRF_ISP_MIPI_CSI_HOST_SEL, 1); 1044} 1045 1046static void rk3399_mipidphy_individual_init(struct mipidphy_priv *priv) 1047{ 1048 /* 1049 * According to the sequence of RK3399_TXRX_DPHY, the setting of isp0 mipi 1050 * will affect txrx dphy in default state of grf_soc_con24. 1051 */ 1052 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0); 1053 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0); 1054 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 0); 1055 1056 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1); 1057} 1058 1059static void rv1126_mipidphy_individual_init(struct mipidphy_priv *priv) 1060{ 1061 struct device *dev = priv->dev; 1062 struct device_node *parent = dev->of_node; 1063 struct device_node *remote = NULL; 1064 u8 val, sel; 1065 1066 priv->grf_regs = priv->phy_index ? rv1126_grf_dphy1_regs : rv1126_grf_dphy0_regs; 1067 val = read_grf_reg(priv, GRF_DPHY_SEL); 1068 /* get port1 remote endpoint info */ 1069 remote = of_graph_get_remote_node(parent, 1, 0); 1070 if (remote) { 1071 if (strstr(remote->name, "isp")) { 1072 sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_ISP; 1073 } else { 1074 sel = !priv->phy_index ? 0 : RV1126_GRF_PHY1_SEL_CIF | RV1126_GRF_PHY1_SEL_CIFLITE; 1075 } 1076 of_node_put(remote); 1077 write_grf_reg(priv, GRF_DPHY_SEL, val | sel); 1078 } 1079} 1080 1081static int mipidphy_rx_stream_on(struct mipidphy_priv *priv, struct v4l2_subdev *sd) 1082{ 1083 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd); 1084 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd); 1085 const struct dphy_drv_data *drv_data = priv->drv_data; 1086 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges; 1087 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges; 1088 int i, hsfreq = 0; 1089 1090 for (i = 0; i < num_hsfreq_ranges; i++) { 1091 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) { 1092 hsfreq = hsfreq_ranges[i].cfg_bit; 1093 break; 1094 } 1095 } 1096 1097 if (i == num_hsfreq_ranges) { 1098 i = num_hsfreq_ranges - 1; 1099 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", priv->data_rate_mbps, 1100 hsfreq_ranges[i].range_h + 1); 1101 hsfreq = hsfreq_ranges[i].cfg_bit; 1102 } 1103 1104 /* RK3288 isp connected to phy0-rx */ 1105 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 0); 1106 1107 /* Belowed is the sequence of mipi configuration */ 1108 /* Step1: set RSTZ = 1'b0, phy0 controlled by isp0 */ 1109 1110 /* Step2: set SHUTDOWNZ = 1'b0, controlled by isp0 */ 1111 1112 /* Step3: set TESTCLEAR = 1'b1 */ 1113 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLK, 1); 1114 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 1); 1115 usleep_range(0x64, 0x96); 1116 1117 /* Step4: apply REFCLK signal with the appropriate frequency */ 1118 1119 /* Step5: apply CFG_CLK signal with the appropriate frequency */ 1120 1121 /* Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE), phy0 default is slave */ 1122 1123 /* Step7: set BASEDIR_N = 1’b1 (for SLAVE), phy0 default is slave */ 1124 1125 /* 1126 * Step8: set all REQUEST inputs to zero, need to wait 15ns: 1127 * step8.1:set lan turndisab as 1 1128 * step8.2:set lan turnrequest as 0 1129 */ 1130 write_grf_reg(priv, GRF_DPHY_RX0_TURNDISABLE, 0xf); 1131 write_grf_reg(priv, GRF_DPHY_RX0_FORCERXMODE, 0); 1132 write_grf_reg(priv, GRF_DPHY_RX0_TURNREQUEST, 0); 1133 usleep_range(0x64, 0x96); 1134 1135 /* Step9: set TESTCLR to low, need to wait 15ns */ 1136 write_grf_reg(priv, GRF_DPHY_RX0_TESTCLR, 0); 1137 usleep_range(0x64, 0x96); 1138 1139 /* 1140 * Step10: configure Test Code 0x44 hsfreqrange according to values 1141 * step10.1:set clock lane 1142 * step10.2:set hsfreqrange by lane0(test code 0x44) 1143 */ 1144 hsfreq <<= 1; 1145 mipidphy0_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0); 1146 mipidphy0_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq); 1147 mipidphy0_wr_reg(priv, LANE1_HS_RX_CONTROL, hsfreq); 1148 mipidphy0_wr_reg(priv, LANE2_HS_RX_CONTROL, hsfreq); 1149 mipidphy0_wr_reg(priv, LANE3_HS_RX_CONTROL, hsfreq); 1150 1151 /* Step11: Configure analog references: of Test Code 0x22 */ 1152 1153 /* Step12: Set ENABLE_N=1'b1, need to wait 5ns */ 1154 /* set lane num */ 1155 write_grf_reg(priv, GRF_DPHY_RX0_ENABLE, GENMASK(sensor->lanes - 1, 0)); 1156 1157 /* Step13: Set SHUTDOWNZ=1'b1, controlled by isp need to wait 5ns */ 1158 1159 /* Step14: Set RSTZ=1'b1, controlled by isp */ 1160 1161 /* 1162 * Step15: Wait until STOPSTATEDATA_N & STOPSTATECLK 1163 * outputs are asserted 1164 */ 1165 1166 usleep_range(0x64, 0x96); 1167 1168 return 0; 1169} 1170 1171static int mipidphy_txrx_stream_on(struct mipidphy_priv *priv, struct v4l2_subdev *sd) 1172{ 1173 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd); 1174 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd); 1175 const struct dphy_drv_data *drv_data = priv->drv_data; 1176 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges; 1177 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges; 1178 int i, hsfreq = 0; 1179 1180 for (i = 0; i < num_hsfreq_ranges; i++) { 1181 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) { 1182 hsfreq = hsfreq_ranges[i].cfg_bit; 1183 break; 1184 } 1185 } 1186 1187 if (i == num_hsfreq_ranges) { 1188 i = num_hsfreq_ranges - 1; 1189 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", priv->data_rate_mbps, 1190 hsfreq_ranges[i].range_h + 1); 1191 hsfreq = hsfreq_ranges[i].cfg_bit; 1192 } 1193 1194 /* 1195 * Config rk3288 1196 * step1:rk3288 isp connected to phy1-rx 1197 * step2:rk3288 phy1-rx test bus connected to csi host 1198 * step3:rk3288 phy1-rx source selected as: isp = 1'b1,csi-host = 1'b0 1199 */ 1200 write_grf_reg(priv, GRF_CON_ISP_DPHY_SEL, 1); 1201 write_grf_reg(priv, GRF_DSI_CSI_TESTBUS_SEL, 1); 1202 write_grf_reg(priv, GRF_DPHY_RX1_SRC_SEL, 1); 1203 1204 /* 1205 * Config rk3399： 1206 * step1:rk3399 phy1-rx source selected as:1'b0=isp1,1'b1=isp0 1207 */ 1208 write_grf_reg(priv, GRF_DPHY_TX1RX1_SRC_SEL, 0); 1209 1210 /* Belowed is the sequence of mipi configuration */ 1211 /* Step1: set RSTZ = 1'b0, phy1-rx controlled by isp */ 1212 1213 /* Step2: set SHUTDOWNZ = 1'b0, phy1-rx controlled by isp */ 1214 1215 /* Step3: set TESTCLR= 1'b1,TESTCLK=1'b1 */ 1216 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLR | PHY_TESTCLK); 1217 usleep_range(0x64, 0x96); 1218 1219 /* Step4: apply REFCLK signal with the appropriate frequency */ 1220 1221 /* Step5: apply CFG_CLK signal with the appropriate frequency */ 1222 1223 /* 1224 * Step6: set MASTERSLAVEZ = 1'b0 (for SLAVE), 1225 * phy1 is set as slave,controlled by isp 1226 */ 1227 write_grf_reg(priv, GRF_DPHY_TX1RX1_MASTERSLAVEZ, 0); 1228 1229 /* 1230 * Step7: set BASEDIR_N = 1’b1 (for SLAVE), 1231 * phy1 is set as slave,controlled by isp 1232 */ 1233 write_grf_reg(priv, GRF_DPHY_TX1RX1_BASEDIR, 1); 1234 1235 /* Step8: set all REQUEST inputs to zero, need to wait 15ns */ 1236 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCERXMODE, 0); 1237 write_grf_reg(priv, GRF_DPHY_TX1RX1_FORCETXSTOPMODE, 0); 1238 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNREQUEST, 0); 1239 write_grf_reg(priv, GRF_DPHY_TX1RX1_TURNDISABLE, 0xf); 1240 usleep_range(0x64, 0x96); 1241 1242 /* Step9: set TESTCLR=1'b0,TESTCLK=1'b1 need to wait 15ns */ 1243 write_txrx_reg(priv, TXRX_PHY_TEST_CTRL0, PHY_TESTCLK); 1244 usleep_range(0x64, 0x96); 1245 1246 /* 1247 * Step10: configure Test Code 0x44 hsfreqrange according to values 1248 * step10.1:set clock lane 1249 * step10.2:set hsfreqrange by lane0(test code 0x44) 1250 */ 1251 hsfreq <<= 1; 1252 mipidphy1_wr_reg(priv, CLOCK_LANE_HS_RX_CONTROL, 0); 1253 mipidphy1_wr_reg(priv, LANE0_HS_RX_CONTROL, hsfreq); 1254 mipidphy1_wr_reg(priv, LANE1_HS_RX_CONTROL, 0); 1255 mipidphy1_wr_reg(priv, LANE2_HS_RX_CONTROL, 0); 1256 mipidphy1_wr_reg(priv, LANE3_HS_RX_CONTROL, 0); 1257 1258 /* Step11: Configure analog references: of Test Code 0x22 */ 1259 1260 /* 1261 * Step12: Set ENABLE_N=1'b1, need to wait 5ns 1262 * Set lane num: 1263 * for 3288,controlled by isp,enable lanes actually 1264 * is set by grf_soc_con9[12:15]; 1265 * for 3399,controlled by isp1,enable lanes actually 1266 * is set by isp1, 1267 * if run 3399 here operates grf_soc_con23[0:3] 1268 */ 1269 write_grf_reg(priv, GRF_DPHY_TX1RX1_ENABLE, GENMASK(sensor->lanes - 1, 0)); 1270 1271 /* 1272 * Step13:Set SHUTDOWNZ=1'b1, phy1-rx controlled by isp, 1273 * need to wait 5ns 1274 */ 1275 1276 /* Step14:Set RSTZ=1'b1, phy1-rx controlled by isp */ 1277 1278 /* 1279 * Step15:Wait until STOPSTATEDATA_N & STOPSTATECLK 1280 * outputs are asserted 1281 */ 1282 1283 usleep_range(0x64, 0x96); 1284 1285 return 0; 1286} 1287 1288static int csi_mipidphy_stream_on(struct mipidphy_priv *priv, struct v4l2_subdev *sd) 1289{ 1290 struct v4l2_subdev *sensor_sd = get_remote_sensor(sd); 1291 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sensor_sd); 1292 const struct dphy_drv_data *drv_data = priv->drv_data; 1293 const struct hsfreq_range *hsfreq_ranges = drv_data->hsfreq_ranges; 1294 int num_hsfreq_ranges = drv_data->num_hsfreq_ranges; 1295 int i, hsfreq = 0; 1296 u32 val = 0; 1297 1298 write_grf_reg(priv, GRF_DVP_V18SEL, 0x1); 1299 1300 /* phy start */ 1301 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe4); 1302 1303 /* set data lane num and enable clock lane */ 1304 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE, 1305 ((GENMASK(sensor->lanes - 1, 0) << MIPI_CSI_DPHY_CTRL_DATALANE_ENABLE_OFFSET_BIT) | 1306 (0x1 << MIPI_CSI_DPHY_CTRL_CLKLANE_ENABLE_OFFSET_BIT) | 0x1)); 1307 1308 /* Reset dphy analog part */ 1309 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe0); 1310 usleep_range(0x1F4, 0x3E8); 1311 1312 if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY) { 1313 /* Reset dphy digital part */ 1314 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1e); 1315 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x1f); 1316 } else { 1317 /* Disable MIPI internal logical and switch to LVDS bank */ 1318 write_csiphy_reg(priv, CSIPHY_CTRL_DIG_RST, 0x3e); 1319 /* Enable LVDS mode */ 1320 write_csiphy_reg(priv, CSIPHY_MIPI_LVDS_MODEL, 0x4); 1321 switch (sensor->format.code) { 1322 case MEDIA_BUS_FMT_Y12_1X12: 1323 case MEDIA_BUS_FMT_SRGGB12_1X12: 1324 case MEDIA_BUS_FMT_SBGGR12_1X12: 1325 case MEDIA_BUS_FMT_SGBRG12_1X12: 1326 case MEDIA_BUS_FMT_SGRBG12_1X12: 1327 val = 0x1f; // 12bit 1328 break; 1329 case MEDIA_BUS_FMT_Y10_1X10: 1330 case MEDIA_BUS_FMT_SBGGR10_1X10: 1331 case MEDIA_BUS_FMT_SRGGB10_1X10: 1332 case MEDIA_BUS_FMT_SGBRG10_1X10: 1333 case MEDIA_BUS_FMT_SGRBG10_1X10: 1334 val = 0xf; // 10bit 1335 break; 1336 default: 1337 val = 0x2f; // 8bit 1338 } 1339 /* Enable LVDS internal logical and select bit mode */ 1340 write_csiphy_reg(priv, CSIPHY_LVDS_MODE, val); 1341 } 1342 1343 /* not into receive mode/wait stopstate */ 1344 write_grf_reg(priv, GRF_DPHY_CSIPHY_FORCERXMODE, 0x0); 1345 1346 /* enable calibration */ 1347 if (priv->data_rate_mbps > 0x5DC) { 1348 write_csiphy_reg(priv, CSIPHY_CLK_CALIB_ENABLE, 0x80); 1349 if (sensor->lanes > 0x00) { 1350 write_csiphy_reg(priv, CSIPHY_LANE0_CALIB_ENABLE, 0x80); 1351 } 1352 if (sensor->lanes > 0x01) { 1353 write_csiphy_reg(priv, CSIPHY_LANE1_CALIB_ENABLE, 0x80); 1354 } 1355 if (sensor->lanes > 0x02) { 1356 write_csiphy_reg(priv, CSIPHY_LANE2_CALIB_ENABLE, 0x80); 1357 } 1358 if (sensor->lanes > 0x03) { 1359 write_csiphy_reg(priv, CSIPHY_LANE3_CALIB_ENABLE, 0x80); 1360 } 1361 } 1362 1363 /* set clock lane and data lane */ 1364 for (i = 0; i < num_hsfreq_ranges; i++) { 1365 if (hsfreq_ranges[i].range_h >= priv->data_rate_mbps) { 1366 hsfreq = hsfreq_ranges[i].cfg_bit; 1367 break; 1368 } 1369 } 1370 1371 if (i == num_hsfreq_ranges) { 1372 i = num_hsfreq_ranges - 1; 1373 dev_warn(priv->dev, "data rate: %lld mbps, max support %d mbps", priv->data_rate_mbps, 1374 hsfreq_ranges[i].range_h + 1); 1375 hsfreq = hsfreq_ranges[i].cfg_bit; 1376 } 1377 1378 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_CLOCK); 1379 if (sensor->lanes > 0x00) { 1380 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA0); 1381 } 1382 if (sensor->lanes > 0x01) { 1383 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA1); 1384 } 1385 if (sensor->lanes > 0x02) { 1386 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA2); 1387 } 1388 if (sensor->lanes > 0x03) { 1389 csi_mipidphy_wr_ths_settle(priv, hsfreq, MIPI_DPHY_LANE_DATA3); 1390 } 1391 1392 write_grf_reg(priv, GRF_DPHY_CLK_INV_SEL, 0x1); 1393 write_grf_reg(priv, GRF_DPHY_CSIPHY_CLKLANE_EN, 0x1); 1394 write_grf_reg(priv, GRF_DPHY_CSIPHY_DATALANE_EN, GENMASK(sensor->lanes - 1, 0)); 1395 return 0; 1396} 1397 1398static int csi_mipidphy_stream_off(struct mipidphy_priv *priv, struct v4l2_subdev *sd) 1399{ 1400 /* disable all lanes */ 1401 write_csiphy_reg(priv, CSIPHY_CTRL_LANE_ENABLE, 0x01); 1402 /* disable pll and ldo */ 1403 write_csiphy_reg(priv, CSIPHY_CTRL_PWRCTL, 0xe3); 1404 usleep_range(0x1F4, 0x3E8); 1405 1406 return 0; 1407} 1408 1409static const struct dphy_drv_data rk1808_mipidphy_drv_data = { 1410 .clks = rk1808_mipidphy_clks, 1411 .num_clks = ARRAY_SIZE(rk1808_mipidphy_clks), 1412 .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges, 1413 .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges), 1414 .grf_regs = rk1808_grf_dphy_regs, 1415 .csiphy_regs = rk1808_csiphy_regs, 1416 .ctl_type = MIPI_DPHY_CTL_CSI_HOST, 1417 .individual_init = default_mipidphy_individual_init, 1418 .chip_id = CHIP_ID_RK1808, 1419}; 1420 1421static const struct dphy_drv_data rk3288_mipidphy_drv_data = { 1422 .clks = rk3288_mipidphy_clks, 1423 .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks), 1424 .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges, 1425 .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges), 1426 .grf_regs = rk3288_grf_dphy_regs, 1427 .txrx_regs = rk3288_txrx_regs, 1428 .ctl_type = MIPI_DPHY_CTL_GRF_ONLY, 1429 .individual_init = default_mipidphy_individual_init, 1430 .chip_id = CHIP_ID_RK3288, 1431}; 1432 1433static const struct dphy_drv_data rk3326_mipidphy_drv_data = { 1434 .clks = rk3326_mipidphy_clks, 1435 .num_clks = ARRAY_SIZE(rk3326_mipidphy_clks), 1436 .hsfreq_ranges = rk3326_mipidphy_hsfreq_ranges, 1437 .num_hsfreq_ranges = ARRAY_SIZE(rk3326_mipidphy_hsfreq_ranges), 1438 .grf_regs = rk3326_grf_dphy_regs, 1439 .csiphy_regs = rk3326_csiphy_regs, 1440 .ctl_type = MIPI_DPHY_CTL_CSI_HOST, 1441 .individual_init = default_mipidphy_individual_init, 1442 .chip_id = CHIP_ID_RK3326, 1443}; 1444 1445static const struct dphy_drv_data rk3368_mipidphy_drv_data = { 1446 .clks = rk3368_mipidphy_clks, 1447 .num_clks = ARRAY_SIZE(rk3368_mipidphy_clks), 1448 .hsfreq_ranges = rk3368_mipidphy_hsfreq_ranges, 1449 .num_hsfreq_ranges = ARRAY_SIZE(rk3368_mipidphy_hsfreq_ranges), 1450 .grf_regs = rk3368_grf_dphy_regs, 1451 .csiphy_regs = rk3368_csiphy_regs, 1452 .ctl_type = MIPI_DPHY_CTL_CSI_HOST, 1453 .individual_init = rk3368_mipidphy_individual_init, 1454 .chip_id = CHIP_ID_RK3368, 1455}; 1456 1457static const struct dphy_drv_data rk3399_mipidphy_drv_data = { 1458 .clks = rk3399_mipidphy_clks, 1459 .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks), 1460 .hsfreq_ranges = rk3399_mipidphy_hsfreq_ranges, 1461 .num_hsfreq_ranges = ARRAY_SIZE(rk3399_mipidphy_hsfreq_ranges), 1462 .grf_regs = rk3399_grf_dphy_regs, 1463 .txrx_regs = rk3399_txrx_regs, 1464 .ctl_type = MIPI_DPHY_CTL_GRF_ONLY, 1465 .individual_init = rk3399_mipidphy_individual_init, 1466 .chip_id = CHIP_ID_RK3399, 1467}; 1468 1469static const struct dphy_drv_data rv1126_mipidphy_drv_data = { 1470 .clks = rv1126_mipidphy_clks, 1471 .num_clks = ARRAY_SIZE(rv1126_mipidphy_clks), 1472 .hsfreq_ranges = rk1808_rv1126_mipidphy_hsfreq_ranges, 1473 .num_hsfreq_ranges = ARRAY_SIZE(rk1808_rv1126_mipidphy_hsfreq_ranges), 1474 .csiphy_regs = rv1126_csiphy_regs, 1475 .ctl_type = MIPI_DPHY_CTL_CSI_HOST, 1476 .individual_init = rv1126_mipidphy_individual_init, 1477 .chip_id = CHIP_ID_RK1126, 1478}; 1479 1480static const struct of_device_id rockchip_mipidphy_match_id[] = {{ 1481 .compatible = "rockchip,rk1808-mipi-dphy-rx", 1482 .data = &rk1808_mipidphy_drv_data, 1483}, { 1484 .compatible = "rockchip,rk3288-mipi-dphy", 1485 .data = &rk3288_mipidphy_drv_data, 1486}, { 1487 .compatible = "rockchip,rk3326-mipi-dphy", 1488 .data = &rk3326_mipidphy_drv_data, 1489}, { 1490 .compatible = "rockchip,rk3368-mipi-dphy", 1491 .data = &rk3368_mipidphy_drv_data, 1492}, { 1493 .compatible = "rockchip,rk3399-mipi-dphy", 1494 .data = &rk3399_mipidphy_drv_data, 1495}, { 1496 .compatible = "rockchip,rv1126-csi-dphy", 1497 .data = &rv1126_mipidphy_drv_data, 1498}, { 1499}}; 1500MODULE_DEVICE_TABLE(of, rockchip_mipidphy_match_id); 1501 1502/* The .bound() notifier callback when a match is found */ 1503static int rockchip_mipidphy_notifier_bound(struct v4l2_async_notifier *notifier, struct v4l2_subdev *sd, 1504 struct v4l2_async_subdev *asd) 1505{ 1506 struct mipidphy_priv *priv = container_of(notifier, struct mipidphy_priv, notifier); 1507 struct sensor_async_subdev *s_asd = container_of(asd, struct sensor_async_subdev, asd); 1508 struct mipidphy_sensor *sensor; 1509 unsigned int pad, ret; 1510 1511 if (priv->num_sensors == ARRAY_SIZE(priv->sensors)) { 1512 return -EBUSY; 1513 } 1514 1515 sensor = &priv->sensors[priv->num_sensors++]; 1516 sensor->lanes = s_asd->lanes; 1517 sensor->mbus = s_asd->mbus; 1518 sensor->sd = sd; 1519 dev_info(priv->dev, "match %s:bus type %d\n", sd->name, s_asd->mbus.type); 1520 1521 for (pad = 0; pad < sensor->sd->entity.num_pads; pad++) { 1522 if (sensor->sd->entity.pads[pad].flags & MEDIA_PAD_FL_SOURCE) { 1523 break; 1524 } 1525 } 1526 1527 if (pad == sensor->sd->entity.num_pads) { 1528 dev_err(priv->dev, "failed to find src pad for %s\n", sensor->sd->name); 1529 1530 return -ENXIO; 1531 } 1532 1533 ret = media_create_pad_link(&sensor->sd->entity, pad, &priv->sd.entity, MIPI_DPHY_RX_PAD_SINK, 1534 priv->num_sensors != 1 ? 0 : MEDIA_LNK_FL_ENABLED); 1535 if (ret) { 1536 dev_err(priv->dev, "failed to create link for %s\n", sensor->sd->name); 1537 return ret; 1538 } 1539 1540 return 0; 1541} 1542 1543/* The .unbind callback */ 1544static void rockchip_mipidphy_notifier_unbind(struct v4l2_async_notifier *notifier, struct v4l2_subdev *sd, 1545 struct v4l2_async_subdev *asd) 1546{ 1547 struct mipidphy_priv *priv = container_of(notifier, struct mipidphy_priv, notifier); 1548 struct mipidphy_sensor *sensor = sd_to_sensor(priv, sd); 1549 1550 sensor->sd = NULL; 1551} 1552 1553static const struct v4l2_async_notifier_operations rockchip_mipidphy_async_ops = { 1554 .bound = rockchip_mipidphy_notifier_bound, 1555 .unbind = rockchip_mipidphy_notifier_unbind, 1556}; 1557 1558static int rockchip_mipidphy_fwnode_parse(struct device *dev, struct v4l2_fwnode_endpoint *vep, 1559 struct v4l2_async_subdev *asd) 1560{ 1561 struct sensor_async_subdev *s_asd = container_of(asd, struct sensor_async_subdev, asd); 1562 struct v4l2_mbus_config *config = &s_asd->mbus; 1563 1564 if (vep->base.port != 0) { 1565 dev_err(dev, "The PHY has only port 0\n"); 1566 return -EINVAL; 1567 } 1568 1569 if (vep->bus_type == V4L2_MBUS_CSI2_DPHY) { 1570 config->type = V4L2_MBUS_CSI2_DPHY; 1571 config->flags = vep->bus.mipi_csi2.flags; 1572 s_asd->lanes = vep->bus.mipi_csi2.num_data_lanes; 1573 } else if (vep->bus_type == V4L2_MBUS_CCP2) { 1574 /* V4L2_MBUS_CCP2 for lvds */ 1575 config->type = V4L2_MBUS_CCP2; 1576 s_asd->lanes = vep->bus.mipi_csi1.data_lane; 1577 } else { 1578 dev_err(dev, "Only CSI2 and CCP2 bus type is currently supported\n"); 1579 return -EINVAL; 1580 } 1581 1582 switch (s_asd->lanes) { 1583 case 1: 1584 config->flags |= V4L2_MBUS_CSI2_1_LANE; 1585 break; 1586 case 0x02: 1587 config->flags |= V4L2_MBUS_CSI2_2_LANE; 1588 break; 1589 case 0x03: 1590 config->flags |= V4L2_MBUS_CSI2_3_LANE; 1591 break; 1592 case 0x04: 1593 config->flags |= V4L2_MBUS_CSI2_4_LANE; 1594 break; 1595 default: 1596 return -EINVAL; 1597 } 1598 1599 return 0; 1600} 1601 1602static int rockchip_mipidphy_media_init(struct mipidphy_priv *priv) 1603{ 1604 int ret; 1605 1606 priv->pads[MIPI_DPHY_RX_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE | MEDIA_PAD_FL_MUST_CONNECT; 1607 priv->pads[MIPI_DPHY_RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK | MEDIA_PAD_FL_MUST_CONNECT; 1608 priv->sd.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; 1609 ret = media_entity_pads_init(&priv->sd.entity, MIPI_DPHY_RX_PADS_NUM, priv->pads); 1610 if (ret < 0) { 1611 return ret; 1612 } 1613 1614 v4l2_async_notifier_init(&priv->notifier); 1615 1616 ret = v4l2_async_notifier_parse_fwnode_endpoints_by_port( 1617 priv->dev, &priv->notifier, sizeof(struct sensor_async_subdev), 0, rockchip_mipidphy_fwnode_parse); 1618 if (ret < 0) { 1619 return ret; 1620 } 1621 1622 priv->sd.subdev_notifier = &priv->notifier; 1623 priv->notifier.ops = &rockchip_mipidphy_async_ops; 1624 ret = v4l2_async_subdev_notifier_register(&priv->sd, &priv->notifier); 1625 if (ret) { 1626 dev_err(priv->dev, "failed to register async notifier : %d\n", ret); 1627 v4l2_async_notifier_cleanup(&priv->notifier); 1628 return ret; 1629 } 1630 1631 return v4l2_async_register_subdev(&priv->sd); 1632} 1633 1634static int rockchip_mipidphy_probe(struct platform_device *pdev) 1635{ 1636 struct device *dev = &pdev->dev; 1637 struct v4l2_subdev *sd; 1638 struct mipidphy_priv *priv; 1639 struct regmap *grf; 1640 struct resource *res; 1641 const struct of_device_id *of_id; 1642 const struct dphy_drv_data *drv_data; 1643 int i, ret; 1644 1645 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1646 if (!priv) { 1647 return -ENOMEM; 1648 } 1649 priv->dev = dev; 1650 1651 of_id = of_match_device(rockchip_mipidphy_match_id, dev); 1652 if (!of_id) { 1653 return -EINVAL; 1654 } 1655 1656 grf = syscon_node_to_regmap(dev->parent->of_node); 1657 if (IS_ERR(grf)) { 1658 grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); 1659 if (IS_ERR(grf)) { 1660 dev_err(dev, "Can't find GRF syscon\n"); 1661 return -ENODEV; 1662 } 1663 } 1664 priv->regmap_grf = grf; 1665 1666 priv->phy_index = of_alias_get_id(dev->of_node, "dphy"); 1667 if (priv->phy_index < 0) { 1668 priv->phy_index = 0; 1669 } 1670 1671 drv_data = of_id->data; 1672 for (i = 0; i < drv_data->num_clks; i++) { 1673 priv->clks[i] = devm_clk_get(dev, drv_data->clks[i]); 1674 1675 if (IS_ERR(priv->clks[i])) { 1676 dev_dbg(dev, "Failed to get %s\n", drv_data->clks[i]); 1677 } 1678 } 1679 1680 priv->grf_regs = drv_data->grf_regs; 1681 priv->txrx_regs = drv_data->txrx_regs; 1682 priv->csiphy_regs = drv_data->csiphy_regs; 1683 priv->drv_data = drv_data; 1684 if (drv_data->ctl_type == MIPI_DPHY_CTL_CSI_HOST) { 1685 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1686 priv->csihost_base_addr = devm_ioremap_resource(dev, res); 1687 priv->stream_on = csi_mipidphy_stream_on; 1688 priv->stream_off = csi_mipidphy_stream_off; 1689 } else { 1690 priv->stream_on = mipidphy_txrx_stream_on; 1691 priv->txrx_base_addr = NULL; 1692 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1693 priv->txrx_base_addr = devm_ioremap_resource(dev, res); 1694 if (IS_ERR(priv->txrx_base_addr)) { 1695 priv->stream_on = mipidphy_rx_stream_on; 1696 } 1697 priv->stream_off = NULL; 1698 } 1699 1700 sd = &priv->sd; 1701 mutex_init(&priv->mutex); 1702 v4l2_subdev_init(sd, &mipidphy_subdev_ops); 1703 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; 1704 snprintf(sd->name, sizeof(sd->name), "rockchip-mipi-dphy-rx"); 1705 sd->dev = dev; 1706 1707 platform_set_drvdata(pdev, &sd->entity); 1708 1709 ret = rockchip_mipidphy_media_init(priv); 1710 if (ret < 0) { 1711 goto destroy_mutex; 1712 } 1713 1714 pm_runtime_enable(&pdev->dev); 1715 drv_data->individual_init(priv); 1716 return 0; 1717 1718destroy_mutex: 1719 mutex_destroy(&priv->mutex); 1720 return 0; 1721} 1722 1723static int rockchip_mipidphy_remove(struct platform_device *pdev) 1724{ 1725 struct media_entity *me = platform_get_drvdata(pdev); 1726 struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(me); 1727 struct mipidphy_priv *priv = platform_get_drvdata(pdev); 1728 1729 media_entity_cleanup(&sd->entity); 1730 1731 pm_runtime_disable(&pdev->dev); 1732 mutex_destroy(&priv->mutex); 1733 return 0; 1734} 1735 1736static const struct dev_pm_ops rockchip_mipidphy_pm_ops = { 1737 SET_RUNTIME_PM_OPS(mipidphy_runtime_suspend, mipidphy_runtime_resume, NULL)}; 1738 1739static struct platform_driver rockchip_isp_mipidphy_driver = { 1740 .probe = rockchip_mipidphy_probe, 1741 .remove = rockchip_mipidphy_remove, 1742 .driver = 1743 { 1744 .name = "rockchip-mipi-dphy-rx", 1745 .pm = &rockchip_mipidphy_pm_ops, 1746 .of_match_table = rockchip_mipidphy_match_id, 1747 }, 1748}; 1749 1750module_platform_driver(rockchip_isp_mipidphy_driver); 1751MODULE_AUTHOR("Rockchip Camera/ISP team"); 1752MODULE_DESCRIPTION("Rockchip MIPI RX DPHY driver"); 1753MODULE_LICENSE("Dual BSD/GPL"); 1754