1/* SPDX-License-Identifier: ((GPL-2.0+ WITH Linux-syscall-note) OR MIT) 2 * 3 * Rockchip isp2 driver 4 * Copyright (C) 2017 Rockchip Electronics Co., Ltd. 5 */ 6 7#ifndef _UAPI_RKISP2_CONFIG_H 8#define _UAPI_RKISP2_CONFIG_H 9 10#include <linux/types.h> 11#include <linux/v4l2-controls.h> 12 13#define RKISP_API_VERSION KERNEL_VERSION(1, 8, 0) 14 15/****************ISP SUBDEV IOCTL*****************************/ 16 17#define RKISP_CMD_TRIGGER_READ_BACK _IOW('V', BASE_VIDIOC_PRIVATE + 0, struct isp2x_csi_trigger) 18 19#define RKISP_CMD_GET_SHARED_BUF _IOR('V', BASE_VIDIOC_PRIVATE + 2, struct rkisp_thunderboot_resmem) 20 21#define RKISP_CMD_FREE_SHARED_BUF _IO('V', BASE_VIDIOC_PRIVATE + 3) 22 23#define RKISP_CMD_GET_LDCHBUF_INFO _IOR('V', BASE_VIDIOC_PRIVATE + 4, struct rkisp_ldchbuf_info) 24 25#define RKISP_CMD_SET_LDCHBUF_SIZE _IOW('V', BASE_VIDIOC_PRIVATE + 5, struct rkisp_ldchbuf_size) 26 27#define RKISP_CMD_GET_SHM_BUFFD _IOWR('V', BASE_VIDIOC_PRIVATE + 6, struct rkisp_thunderboot_shmem) 28 29#define RKISP_CMD_GET_FBCBUF_FD _IOR('V', BASE_VIDIOC_PRIVATE + 7, struct isp2x_buf_idxfd) 30 31#define RKISP_CMD_GET_MESHBUF_INFO _IOWR('V', BASE_VIDIOC_PRIVATE + 8, struct rkisp_meshbuf_info) 32 33#define RKISP_CMD_SET_MESHBUF_SIZE _IOW('V', BASE_VIDIOC_PRIVATE + 9, struct rkisp_meshbuf_size) 34 35/****************ISP VIDEO IOCTL******************************/ 36 37#define RKISP_CMD_GET_CSI_MEMORY_MODE _IOR('V', BASE_VIDIOC_PRIVATE + 100, int) 38 39#define RKISP_CMD_SET_CSI_MEMORY_MODE _IOW('V', BASE_VIDIOC_PRIVATE + 101, int) 40 41#define RKISP_CMD_GET_CMSK _IOR('V', BASE_VIDIOC_PRIVATE + 102, struct rkisp_cmsk_cfg) 42 43#define RKISP_CMD_SET_CMSK _IOW('V', BASE_VIDIOC_PRIVATE + 103, struct rkisp_cmsk_cfg) 44 45/*************************************************************/ 46 47#define ISP2X_ID_DPCC (0) 48#define ISP2X_ID_BLS (1) 49#define ISP2X_ID_SDG (2) 50#define ISP2X_ID_SIHST (3) 51#define ISP2X_ID_LSC (4) 52#define ISP2X_ID_AWB_GAIN (5) 53#define ISP2X_ID_BDM (7) 54#define ISP2X_ID_CCM (8) 55#define ISP2X_ID_GOC (9) 56#define ISP2X_ID_CPROC (10) 57#define ISP2X_ID_SIAF (11) 58#define ISP2X_ID_SIAWB (12) 59#define ISP2X_ID_IE (13) 60#define ISP2X_ID_YUVAE (14) 61#define ISP2X_ID_WDR (15) 62#define ISP2X_ID_RK_IESHARP (16) 63#define ISP2X_ID_RAWAF (17) 64#define ISP2X_ID_RAWAE0 (18) 65#define ISP2X_ID_RAWAE1 (19) 66#define ISP2X_ID_RAWAE2 (20) 67#define ISP2X_ID_RAWAE3 (21) 68#define ISP2X_ID_RAWAWB (22) 69#define ISP2X_ID_RAWHIST0 (23) 70#define ISP2X_ID_RAWHIST1 (24) 71#define ISP2X_ID_RAWHIST2 (25) 72#define ISP2X_ID_RAWHIST3 (26) 73#define ISP2X_ID_HDRMGE (27) 74#define ISP2X_ID_RAWNR (28) 75#define ISP2X_ID_HDRTMO (29) 76#define ISP2X_ID_GIC (30) 77#define ISP2X_ID_DHAZ (31) 78#define ISP2X_ID_3DLUT (32) 79#define ISP2X_ID_LDCH (33) 80#define ISP2X_ID_GAIN (34) 81#define ISP2X_ID_DEBAYER (35) 82#define ISP2X_ID_MAX (36) 83 84#define ISP2X_MODULE_DPCC BIT_ULL(ISP2X_ID_DPCC) 85#define ISP2X_MODULE_BLS BIT_ULL(ISP2X_ID_BLS) 86#define ISP2X_MODULE_SDG BIT_ULL(ISP2X_ID_SDG) 87#define ISP2X_MODULE_SIHST BIT_ULL(ISP2X_ID_SIHST) 88#define ISP2X_MODULE_LSC BIT_ULL(ISP2X_ID_LSC) 89#define ISP2X_MODULE_AWB_GAIN BIT_ULL(ISP2X_ID_AWB_GAIN) 90#define ISP2X_MODULE_BDM BIT_ULL(ISP2X_ID_BDM) 91#define ISP2X_MODULE_CCM BIT_ULL(ISP2X_ID_CCM) 92#define ISP2X_MODULE_GOC BIT_ULL(ISP2X_ID_GOC) 93#define ISP2X_MODULE_CPROC BIT_ULL(ISP2X_ID_CPROC) 94#define ISP2X_MODULE_SIAF BIT_ULL(ISP2X_ID_SIAF) 95#define ISP2X_MODULE_SIAWB BIT_ULL(ISP2X_ID_SIAWB) 96#define ISP2X_MODULE_IE BIT_ULL(ISP2X_ID_IE) 97#define ISP2X_MODULE_YUVAE BIT_ULL(ISP2X_ID_YUVAE) 98#define ISP2X_MODULE_WDR BIT_ULL(ISP2X_ID_WDR) 99#define ISP2X_MODULE_RK_IESHARP BIT_ULL(ISP2X_ID_RK_IESHARP) 100#define ISP2X_MODULE_RAWAF BIT_ULL(ISP2X_ID_RAWAF) 101#define ISP2X_MODULE_RAWAE0 BIT_ULL(ISP2X_ID_RAWAE0) 102#define ISP2X_MODULE_RAWAE1 BIT_ULL(ISP2X_ID_RAWAE1) 103#define ISP2X_MODULE_RAWAE2 BIT_ULL(ISP2X_ID_RAWAE2) 104#define ISP2X_MODULE_RAWAE3 BIT_ULL(ISP2X_ID_RAWAE3) 105#define ISP2X_MODULE_RAWAWB BIT_ULL(ISP2X_ID_RAWAWB) 106#define ISP2X_MODULE_RAWHIST0 BIT_ULL(ISP2X_ID_RAWHIST0) 107#define ISP2X_MODULE_RAWHIST1 BIT_ULL(ISP2X_ID_RAWHIST1) 108#define ISP2X_MODULE_RAWHIST2 BIT_ULL(ISP2X_ID_RAWHIST2) 109#define ISP2X_MODULE_RAWHIST3 BIT_ULL(ISP2X_ID_RAWHIST3) 110#define ISP2X_MODULE_HDRMGE BIT_ULL(ISP2X_ID_HDRMGE) 111#define ISP2X_MODULE_RAWNR BIT_ULL(ISP2X_ID_RAWNR) 112#define ISP2X_MODULE_HDRTMO BIT_ULL(ISP2X_ID_HDRTMO) 113#define ISP2X_MODULE_GIC BIT_ULL(ISP2X_ID_GIC) 114#define ISP2X_MODULE_DHAZ BIT_ULL(ISP2X_ID_DHAZ) 115#define ISP2X_MODULE_3DLUT BIT_ULL(ISP2X_ID_3DLUT) 116#define ISP2X_MODULE_LDCH BIT_ULL(ISP2X_ID_LDCH) 117#define ISP2X_MODULE_GAIN BIT_ULL(ISP2X_ID_GAIN) 118#define ISP2X_MODULE_DEBAYER BIT_ULL(ISP2X_ID_DEBAYER) 119 120/* 121 * Measurement types 122 */ 123#define ISP2X_STAT_SIAWB BIT(0) 124#define ISP2X_STAT_YUVAE BIT(1) 125#define ISP2X_STAT_SIAF BIT(2) 126#define ISP2X_STAT_SIHST BIT(3) 127#define ISP2X_STAT_EMB_DATA BIT(4) 128#define ISP2X_STAT_RAWAWB BIT(5) 129#define ISP2X_STAT_RAWAF BIT(6) 130#define ISP2X_STAT_RAWAE0 BIT(7) 131#define ISP2X_STAT_RAWAE1 BIT(8) 132#define ISP2X_STAT_RAWAE2 BIT(9) 133#define ISP2X_STAT_RAWAE3 BIT(10) 134#define ISP2X_STAT_RAWHST0 BIT(11) 135#define ISP2X_STAT_RAWHST1 BIT(12) 136#define ISP2X_STAT_RAWHST2 BIT(13) 137#define ISP2X_STAT_RAWHST3 BIT(14) 138#define ISP2X_STAT_BLS BIT(15) 139#define ISP2X_STAT_HDRTMO BIT(16) 140#define ISP2X_STAT_DHAZ BIT(17) 141 142#define ISP2X_LSC_GRAD_TBL_SIZE 8 143#define ISP2X_LSC_SIZE_TBL_SIZE 8 144#define ISP2X_LSC_DATA_TBL_SIZE 290 145 146#define ISP2X_DEGAMMA_CURVE_SIZE 17 147 148#define ISP2X_GAIN_HDRMGE_GAIN_NUM 3 149#define ISP2X_GAIN_IDX_NUM 15 150#define ISP2X_GAIN_LUT_NUM 17 151 152#define ISP2X_AWB_MAX_GRID 1 153#define ISP2X_RAWAWB_SUM_NUM 7 154#define ISP2X_RAWAWB_MULWD_NUM 8 155#define ISP2X_RAWAWB_RAMDATA_NUM 225 156 157#define ISP2X_RAWAEBIG_SUBWIN_NUM 4 158#define ISP2X_RAWAEBIG_MEAN_NUM 225 159#define ISP2X_RAWAELITE_MEAN_NUM 25 160#define ISP2X_YUVAE_SUBWIN_NUM 4 161#define ISP2X_YUVAE_MEAN_NUM 225 162 163#define ISP2X_RAWHISTBIG_SUBWIN_NUM 225 164#define ISP2X_RAWHISTLITE_SUBWIN_NUM 25 165#define ISP2X_SIHIST_WIN_NUM 1 166#define ISP2X_HIST_WEIGHT_NUM 225 167#define ISP2X_HIST_BIN_N_MAX 256 168#define ISP2X_SIHIST_BIN_N_MAX 32 169 170#define ISP2X_RAWAF_WIN_NUM 2 171#define ISP2X_RAWAF_LINE_NUM 5 172#define ISP2X_RAWAF_GAMMA_NUM 17 173#define ISP2X_RAWAF_SUMDATA_ROW 15 174#define ISP2X_RAWAF_SUMDATA_COLUMN 15 175#define ISP2X_RAWAF_SUMDATA_NUM 225 176#define ISP2X_AFM_MAX_WINDOWS 3 177 178#define ISP2X_DPCC_PDAF_POINT_NUM 16 179 180#define ISP2X_HDRMGE_L_CURVE_NUM 17 181#define ISP2X_HDRMGE_E_CURVE_NUM 17 182 183#define ISP2X_RAWNR_LUMA_RATION_NUM 8 184 185#define ISP2X_HDRTMO_MINMAX_NUM 32 186 187#define ISP2X_GIC_SIGMA_Y_NUM 15 188 189#define ISP2X_CCM_CURVE_NUM 17 190 191/* WDR */ 192#define ISP2X_WDR_SIZE 48 193 194#define ISP2X_DHAZ_CONV_COEFF_NUM 6 195#define ISP2X_DHAZ_HIST_IIR_NUM 64 196 197#define ISP2X_GAMMA_OUT_MAX_SAMPLES 45 198 199#define ISP2X_MIPI_LUMA_MEAN_MAX 16 200#define ISP2X_MIPI_RAW_MAX 3 201#define ISP2X_RAW0_Y_STATE (1 << 0) 202#define ISP2X_RAW1_Y_STATE (1 << 1) 203#define ISP2X_RAW2_Y_STATE (1 << 2) 204 205#define ISP2X_3DLUT_DATA_NUM 729 206 207#define ISP2X_LDCH_MESH_XY_NUM 0x80000 208#define ISP2X_LDCH_BUF_NUM 2 209 210#define ISP2X_THUNDERBOOT_VIDEO_BUF_NUM 30 211 212#define ISP2X_FBCBUF_FD_NUM 64 213 214#define ISP2X_MESH_BUF_NUM 2 215 216enum isp2x_mesh_buf_stat { 217 MESH_BUF_INIT = 0, 218 MESH_BUF_WAIT2CHIP, 219 MESH_BUF_CHIPINUSE, 220}; 221 222struct rkisp_meshbuf_info { 223 u64 module_id; 224 u32 unite_isp_id; 225 s32 buf_fd[ISP2X_MESH_BUF_NUM]; 226 u32 buf_size[ISP2X_MESH_BUF_NUM]; 227} __attribute__((packed)); 228 229struct rkisp_meshbuf_size { 230 u64 module_id; 231 u32 unite_isp_id; 232 u32 meas_width; 233 u32 meas_height; 234} __attribute__((packed)); 235 236struct isp2x_mesh_head { 237 enum isp2x_mesh_buf_stat stat; 238 u32 data_oft; 239} __attribute__((packed)); 240 241#define RKISP_CMSK_WIN_MAX 8 242#define RKISP_CMSK_MOSAIC_MODE 0 243#define RKISP_CMSK_COVER_MODE 1 244 245/* struct rkisp_cmsk_win 246 * Priacy Mask Window configture, support 8 windows, and 247 * support for mainpath and selfpath output stream channel. 248 * 249 * mode: 0:mosaic mode, 1:cover mode 250 * win_index: window index 0~7. windows overlap, priority win7 > win0. 251 * cover_color_y: cover mode effective, share for stream channel when same win_index. 252 * cover_color_u: cover mode effective, share for stream channel when same win_index. 253 * cover_color_v: cover mode effective, share for stream channel when same win_index. 254 * 255 * h_offs: window horizontal offset, share for stream channel when same win_index. 2 align. 256 * v_offs: window vertical offset, share for stream channel when same win_index. 2 align. 257 * h_size: window horizontal size, share for stream channel when same win_index. 8 align. 258 * v_size: window vertical size, share for stream channel when same win_index. 8 align. 259 */ 260struct rkisp_cmsk_win { 261 unsigned char mode; 262 unsigned char win_en; 263 264 unsigned char cover_color_y; 265 unsigned char cover_color_u; 266 unsigned char cover_color_v; 267 268 unsigned short h_offs; 269 unsigned short v_offs; 270 unsigned short h_size; 271 unsigned short v_size; 272} __attribute__((packed)); 273 274/* struct rkisp_cmsk_cfg 275 * win: priacy mask window 276 * width_ro: isp full resolution, h_offs + h_size <= width_ro. 277 * height_ro: isp full resolution, v_offs + v_size <= height_ro. 278 */ 279struct rkisp_cmsk_cfg { 280 struct rkisp_cmsk_win win[RKISP_CMSK_WIN_MAX]; 281 unsigned int width_ro; 282 unsigned int height_ro; 283} __attribute__((packed)); 284 285/* trigger event mode 286 * T_TRY: trigger maybe with retry 287 * T_TRY_YES: trigger to retry 288 * T_TRY_NO: trigger no to retry 289 * 290 * T_START_X1: isp read one frame 291 * T_START_X2: isp read hdr two frame 292 * T_START_X3: isp read hdr three frame 293 */ 294enum isp2x_trigger_mode { 295 T_TRY = BIT(0), 296 T_TRY_YES = BIT(1), 297 T_TRY_NO = BIT(2), 298 299 T_START_X1 = BIT(4), 300 T_START_X2 = BIT(5), 301 T_START_X3 = BIT(6), 302}; 303 304struct isp2x_csi_trigger { 305 /* timestamp in ns */ 306 u64 sof_timestamp; 307 u64 frame_timestamp; 308 u32 frame_id; 309 int times; 310 enum isp2x_trigger_mode mode; 311} __attribute__((packed)); 312 313/* isp csi dmatx/dmarx memory mode 314 * 0: raw12/raw10/raw8 8bit memory compact 315 * 1: raw12/raw10 16bit memory one pixel 316 * big endian for rv1126/rv1109 317 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 318 * | 3| 2| 1| 0| -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 319 * little align for rk356x 320 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 321 * | -| -| -| -|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 322 * 2: raw12/raw10 16bit memory one pixel 323 * big align for rv1126/rv1109/rk356x 324 * |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| 325 * |11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0| -| -| -| -| 326 */ 327enum isp_csi_memory { 328 CSI_MEM_COMPACT = 0, 329 CSI_MEM_WORD_BIG_END = 1, 330 CSI_MEM_WORD_LITTLE_ALIGN = 1, 331 CSI_MEM_WORD_BIG_ALIGN = 2, 332}; 333 334struct isp2x_ispgain_buf { 335 u32 gain_dmaidx; 336 u32 mfbc_dmaidx; 337 u32 gain_size; 338 u32 mfbc_size; 339 u32 frame_id; 340} __attribute__((packed)); 341 342struct isp2x_buf_idxfd { 343 u32 buf_num; 344 u32 index[ISP2X_FBCBUF_FD_NUM]; 345 s32 dmafd[ISP2X_FBCBUF_FD_NUM]; 346} __attribute__((packed)); 347 348struct isp2x_window { 349 u16 h_offs; 350 u16 v_offs; 351 u16 h_size; 352 u16 v_size; 353} __attribute__((packed)); 354 355struct isp2x_bls_fixed_val { 356 s16 r; 357 s16 gr; 358 s16 gb; 359 s16 b; 360} __attribute__((packed)); 361 362struct isp2x_bls_cfg { 363 u8 enable_auto; 364 u8 en_windows; 365 struct isp2x_window bls_window1; 366 struct isp2x_window bls_window2; 367 u8 bls_samples; 368 struct isp2x_bls_fixed_val fixed_val; 369} __attribute__((packed)); 370 371struct isp2x_bls_stat { 372 u16 meas_r; 373 u16 meas_gr; 374 u16 meas_gb; 375 u16 meas_b; 376} __attribute__((packed)); 377 378struct isp2x_dpcc_pdaf_point { 379 u8 y; 380 u8 x; 381} __attribute__((packed)); 382 383struct isp2x_dpcc_cfg { 384 // mode 0x0000 385 u8 stage1_enable; 386 u8 grayscale_mode; 387 388 // output_mode 0x0004 389 u8 sw_rk_out_sel; 390 u8 sw_dpcc_output_sel; 391 u8 stage1_rb_3x3; 392 u8 stage1_g_3x3; 393 u8 stage1_incl_rb_center; 394 u8 stage1_incl_green_center; 395 396 // set_use 0x0008 397 u8 stage1_use_fix_set; 398 u8 stage1_use_set_3; 399 u8 stage1_use_set_2; 400 u8 stage1_use_set_1; 401 402 // methods_set_1 0x000c 403 u8 sw_rk_red_blue1_en; 404 u8 rg_red_blue1_enable; 405 u8 rnd_red_blue1_enable; 406 u8 ro_red_blue1_enable; 407 u8 lc_red_blue1_enable; 408 u8 pg_red_blue1_enable; 409 u8 sw_rk_green1_en; 410 u8 rg_green1_enable; 411 u8 rnd_green1_enable; 412 u8 ro_green1_enable; 413 u8 lc_green1_enable; 414 u8 pg_green1_enable; 415 416 // methods_set_2 0x0010 417 u8 sw_rk_red_blue2_en; 418 u8 rg_red_blue2_enable; 419 u8 rnd_red_blue2_enable; 420 u8 ro_red_blue2_enable; 421 u8 lc_red_blue2_enable; 422 u8 pg_red_blue2_enable; 423 u8 sw_rk_green2_en; 424 u8 rg_green2_enable; 425 u8 rnd_green2_enable; 426 u8 ro_green2_enable; 427 u8 lc_green2_enable; 428 u8 pg_green2_enable; 429 430 // methods_set_3 0x0014 431 u8 sw_rk_red_blue3_en; 432 u8 rg_red_blue3_enable; 433 u8 rnd_red_blue3_enable; 434 u8 ro_red_blue3_enable; 435 u8 lc_red_blue3_enable; 436 u8 pg_red_blue3_enable; 437 u8 sw_rk_green3_en; 438 u8 rg_green3_enable; 439 u8 rnd_green3_enable; 440 u8 ro_green3_enable; 441 u8 lc_green3_enable; 442 u8 pg_green3_enable; 443 444 // line_thresh_1 0x0018 445 u8 sw_mindis1_rb; 446 u8 sw_mindis1_g; 447 u8 line_thr_1_rb; 448 u8 line_thr_1_g; 449 450 // line_mad_fac_1 0x001c 451 u8 sw_dis_scale_min1; 452 u8 sw_dis_scale_max1; 453 u8 line_mad_fac_1_rb; 454 u8 line_mad_fac_1_g; 455 456 // pg_fac_1 0x0020 457 u8 pg_fac_1_rb; 458 u8 pg_fac_1_g; 459 460 // rnd_thresh_1 0x0024 461 u8 rnd_thr_1_rb; 462 u8 rnd_thr_1_g; 463 464 // rg_fac_1 0x0028 465 u8 rg_fac_1_rb; 466 u8 rg_fac_1_g; 467 468 // line_thresh_2 0x002c 469 u8 sw_mindis2_rb; 470 u8 sw_mindis2_g; 471 u8 line_thr_2_rb; 472 u8 line_thr_2_g; 473 474 // line_mad_fac_2 0x0030 475 u8 sw_dis_scale_min2; 476 u8 sw_dis_scale_max2; 477 u8 line_mad_fac_2_rb; 478 u8 line_mad_fac_2_g; 479 480 // pg_fac_2 0x0034 481 u8 pg_fac_2_rb; 482 u8 pg_fac_2_g; 483 484 // rnd_thresh_2 0x0038 485 u8 rnd_thr_2_rb; 486 u8 rnd_thr_2_g; 487 488 // rg_fac_2 0x003c 489 u8 rg_fac_2_rb; 490 u8 rg_fac_2_g; 491 492 // line_thresh_3 0x0040 493 u8 sw_mindis3_rb; 494 u8 sw_mindis3_g; 495 u8 line_thr_3_rb; 496 u8 line_thr_3_g; 497 498 // line_mad_fac_3 0x0044 499 u8 sw_dis_scale_min3; 500 u8 sw_dis_scale_max3; 501 u8 line_mad_fac_3_rb; 502 u8 line_mad_fac_3_g; 503 504 // pg_fac_3 0x0048 505 u8 pg_fac_3_rb; 506 u8 pg_fac_3_g; 507 508 // rnd_thresh_3 0x004c 509 u8 rnd_thr_3_rb; 510 u8 rnd_thr_3_g; 511 512 // rg_fac_3 0x0050 513 u8 rg_fac_3_rb; 514 u8 rg_fac_3_g; 515 516 // ro_limits 0x0054 517 u8 ro_lim_3_rb; 518 u8 ro_lim_3_g; 519 u8 ro_lim_2_rb; 520 u8 ro_lim_2_g; 521 u8 ro_lim_1_rb; 522 u8 ro_lim_1_g; 523 524 // rnd_offs 0x0058 525 u8 rnd_offs_3_rb; 526 u8 rnd_offs_3_g; 527 u8 rnd_offs_2_rb; 528 u8 rnd_offs_2_g; 529 u8 rnd_offs_1_rb; 530 u8 rnd_offs_1_g; 531 532 // bpt_ctrl 0x005c 533 u8 bpt_rb_3x3; 534 u8 bpt_g_3x3; 535 u8 bpt_incl_rb_center; 536 u8 bpt_incl_green_center; 537 u8 bpt_use_fix_set; 538 u8 bpt_use_set_3; 539 u8 bpt_use_set_2; 540 u8 bpt_use_set_1; 541 u8 bpt_cor_en; 542 u8 bpt_det_en; 543 544 // bpt_number 0x0060 545 u16 bp_number; 546 547 // bpt_addr 0x0064 548 u16 bp_table_addr; 549 550 // bpt_data 0x0068 551 u16 bpt_v_addr; 552 u16 bpt_h_addr; 553 554 // bp_cnt 0x006c 555 u32 bp_cnt; 556 557 // pdaf_en 0x0070 558 u8 sw_pdaf_en; 559 560 // pdaf_point_en 0x0074 561 u8 pdaf_point_en[ISP2X_DPCC_PDAF_POINT_NUM]; 562 563 // pdaf_offset 0x0078 564 u16 pdaf_offsety; 565 u16 pdaf_offsetx; 566 567 // pdaf_wrap 0x007c 568 u16 pdaf_wrapy; 569 u16 pdaf_wrapx; 570 571 // pdaf_scope 0x0080 572 u16 pdaf_wrapy_num; 573 u16 pdaf_wrapx_num; 574 575 // pdaf_point_0 0x0084 576 struct isp2x_dpcc_pdaf_point point[ISP2X_DPCC_PDAF_POINT_NUM]; 577 578 // pdaf_forward_med 0x00a4 579 u8 pdaf_forward_med; 580} __attribute__((packed)); 581 582struct isp2x_hdrmge_curve { 583 u16 curve_1[ISP2X_HDRMGE_L_CURVE_NUM]; 584 u16 curve_0[ISP2X_HDRMGE_L_CURVE_NUM]; 585} __attribute__((packed)); 586 587struct isp2x_hdrmge_cfg { 588 u8 mode; 589 590 u16 gain0_inv; 591 u16 gain0; 592 593 u16 gain1_inv; 594 u16 gain1; 595 596 u8 gain2; 597 598 u8 lm_dif_0p15; 599 u8 lm_dif_0p9; 600 u8 ms_diff_0p15; 601 u8 ms_dif_0p8; 602 603 struct isp2x_hdrmge_curve curve; 604 u16 e_y[ISP2X_HDRMGE_E_CURVE_NUM]; 605} __attribute__((packed)); 606 607struct isp2x_rawnr_cfg { 608 u8 gauss_en; 609 u8 log_bypass; 610 611 u16 filtpar0; 612 u16 filtpar1; 613 u16 filtpar2; 614 615 u32 dgain0; 616 u32 dgain1; 617 u32 dgain2; 618 619 u16 luration[ISP2X_RAWNR_LUMA_RATION_NUM]; 620 u16 lulevel[ISP2X_RAWNR_LUMA_RATION_NUM]; 621 622 u32 gauss; 623 u16 sigma; 624 u16 pix_diff; 625 626 u32 thld_diff; 627 628 u8 gas_weig_scl2; 629 u8 gas_weig_scl1; 630 u16 thld_chanelw; 631 632 u16 lamda; 633 634 u16 fixw0; 635 u16 fixw1; 636 u16 fixw2; 637 u16 fixw3; 638 639 u32 wlamda0; 640 u32 wlamda1; 641 u32 wlamda2; 642 643 u16 rgain_filp; 644 u16 bgain_filp; 645} __attribute__((packed)); 646 647struct isp2x_lsc_cfg { 648 u16 r_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 649 u16 gr_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 650 u16 gb_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 651 u16 b_data_tbl[ISP2X_LSC_DATA_TBL_SIZE]; 652 653 u16 x_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 654 u16 y_grad_tbl[ISP2X_LSC_GRAD_TBL_SIZE]; 655 656 u16 x_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 657 u16 y_size_tbl[ISP2X_LSC_SIZE_TBL_SIZE]; 658} __attribute__((packed)); 659 660enum isp2x_goc_mode { ISP2X_GOC_MODE_LOGARITHMIC, ISP2X_GOC_MODE_EQUIDISTANT }; 661 662struct isp2x_goc_cfg { 663 enum isp2x_goc_mode mode; 664 u8 gamma_y[17]; 665} __attribute__((packed)); 666 667struct isp2x_hdrtmo_predict { 668 u8 global_tmo; 669 s32 iir_max; 670 s32 global_tmo_strength; 671 672 u8 scene_stable; 673 s32 k_rolgmean; 674 s32 iir; 675} __attribute__((packed)); 676 677struct isp2x_hdrtmo_cfg { 678 u16 cnt_vsize; 679 u8 gain_ld_off2; 680 u8 gain_ld_off1; 681 u8 big_en; 682 u8 nobig_en; 683 u8 newhst_en; 684 u8 cnt_mode; 685 686 u16 expl_lgratio; 687 u8 lgscl_ratio; 688 u8 cfg_alpha; 689 690 u16 set_gainoff; 691 u16 set_palpha; 692 693 u16 set_lgmax; 694 u16 set_lgmin; 695 696 u8 set_weightkey; 697 u16 set_lgmean; 698 699 u16 set_lgrange1; 700 u16 set_lgrange0; 701 702 u16 set_lgavgmax; 703 704 u8 clipgap1_i; 705 u8 clipgap0_i; 706 u8 clipratio1; 707 u8 clipratio0; 708 u8 ratiol; 709 710 u16 lgscl_inv; 711 u16 lgscl; 712 713 u16 lgmax; 714 715 u16 hist_low; 716 u16 hist_min; 717 718 u8 hist_shift; 719 u16 hist_0p3; 720 u16 hist_high; 721 722 u16 palpha_lwscl; 723 u16 palpha_lw0p5; 724 u16 palpha_0p18; 725 726 u16 maxgain; 727 u16 maxpalpha; 728 729 struct isp2x_hdrtmo_predict predict; 730} __attribute__((packed)); 731 732struct isp2x_hdrtmo_stat { 733 u16 lglow; 734 u16 lgmin; 735 u16 lghigh; 736 u16 lgmax; 737 u16 weightkey; 738 u16 lgmean; 739 u16 lgrange1; 740 u16 lgrange0; 741 u16 palpha; 742 u16 lgavgmax; 743 u16 linecnt; 744 u32 min_max[ISP2X_HDRTMO_MINMAX_NUM]; 745} __attribute__((packed)); 746 747struct isp2x_gic_cfg { 748 u8 edge_open; 749 750 u16 regmingradthrdark2; 751 u16 regmingradthrdark1; 752 u16 regminbusythre; 753 754 u16 regdarkthre; 755 u16 regmaxcorvboth; 756 u16 regdarktthrehi; 757 758 u8 regkgrad2dark; 759 u8 regkgrad1dark; 760 u8 regstrengthglobal_fix; 761 u8 regdarkthrestep; 762 u8 regkgrad2; 763 u8 regkgrad1; 764 u8 reggbthre; 765 766 u16 regmaxcorv; 767 u16 regmingradthr2; 768 u16 regmingradthr1; 769 770 u8 gr_ratio; 771 u16 dnloscale; 772 u16 dnhiscale; 773 u8 reglumapointsstep; 774 775 u16 gvaluelimitlo; 776 u16 gvaluelimithi; 777 u8 fusionratiohilimt1; 778 779 u8 regstrength_fix; 780 781 u16 sigma_y[ISP2X_GIC_SIGMA_Y_NUM]; 782 783 u8 noise_cut_en; 784 u16 noise_coe_a; 785 786 u16 noise_coe_b; 787 u16 diff_clip; 788} __attribute__((packed)); 789 790struct isp2x_debayer_cfg { 791 u8 filter_c_en; 792 u8 filter_g_en; 793 794 u8 thed1; 795 u8 thed0; 796 u8 dist_scale; 797 u8 max_ratio; 798 u8 clip_en; 799 800 s8 filter1_coe5; 801 s8 filter1_coe4; 802 s8 filter1_coe3; 803 s8 filter1_coe2; 804 s8 filter1_coe1; 805 806 s8 filter2_coe5; 807 s8 filter2_coe4; 808 s8 filter2_coe3; 809 s8 filter2_coe2; 810 s8 filter2_coe1; 811 812 u16 hf_offset; 813 u8 gain_offset; 814 u8 offset; 815 816 u8 shift_num; 817 u8 order_max; 818 u8 order_min; 819} __attribute__((packed)); 820 821struct isp2x_ccm_cfg { 822 s16 coeff0_r; 823 s16 coeff1_r; 824 s16 coeff2_r; 825 s16 offset_r; 826 827 s16 coeff0_g; 828 s16 coeff1_g; 829 s16 coeff2_g; 830 s16 offset_g; 831 832 s16 coeff0_b; 833 s16 coeff1_b; 834 s16 coeff2_b; 835 s16 offset_b; 836 837 u16 coeff0_y; 838 u16 coeff1_y; 839 u16 coeff2_y; 840 841 u16 alp_y[ISP2X_CCM_CURVE_NUM]; 842 843 u8 bound_bit; 844} __attribute__((packed)); 845 846struct isp2x_gammaout_cfg { 847 u8 equ_segm; 848 u16 offset; 849 u16 gamma_y[ISP2X_GAMMA_OUT_MAX_SAMPLES]; 850} __attribute__((packed)); 851 852enum isp2x_wdr_mode { ISP2X_WDR_MODE_BLOCK, ISP2X_WDR_MODE_GLOBAL }; 853 854struct isp2x_wdr_cfg { 855 enum isp2x_wdr_mode mode; 856 unsigned int c_wdr[ISP2X_WDR_SIZE]; 857} __attribute__((packed)); 858 859struct isp2x_dhaz_cfg { 860 u8 enhance_en; 861 u8 hist_chn; 862 u8 hpara_en; 863 u8 hist_en; 864 u8 dc_en; 865 u8 big_en; 866 u8 nobig_en; 867 868 u8 yblk_th; 869 u8 yhist_th; 870 u8 dc_max_th; 871 u8 dc_min_th; 872 873 u16 wt_max; 874 u8 bright_max; 875 u8 bright_min; 876 877 u8 tmax_base; 878 u8 dark_th; 879 u8 air_max; 880 u8 air_min; 881 882 u16 tmax_max; 883 u16 tmax_off; 884 885 u8 hist_th_off; 886 u8 hist_gratio; 887 888 u16 hist_min; 889 u16 hist_k; 890 891 u16 enhance_value; 892 u16 hist_scale; 893 894 u16 iir_wt_sigma; 895 u16 iir_sigma; 896 u16 stab_fnum; 897 898 u16 iir_tmax_sigma; 899 u16 iir_air_sigma; 900 901 u16 cfg_wt; 902 u16 cfg_air; 903 u16 cfg_alpha; 904 905 u16 cfg_gratio; 906 u16 cfg_tmax; 907 908 u16 dc_weitcur; 909 u16 dc_thed; 910 911 u8 sw_dhaz_dc_bf_h3; 912 u8 sw_dhaz_dc_bf_h2; 913 u8 sw_dhaz_dc_bf_h1; 914 u8 sw_dhaz_dc_bf_h0; 915 916 u8 sw_dhaz_dc_bf_h5; 917 u8 sw_dhaz_dc_bf_h4; 918 919 u16 air_weitcur; 920 u16 air_thed; 921 922 u8 air_bf_h2; 923 u8 air_bf_h1; 924 u8 air_bf_h0; 925 926 u8 gaus_h2; 927 u8 gaus_h1; 928 u8 gaus_h0; 929 930 u8 conv_t0[ISP2X_DHAZ_CONV_COEFF_NUM]; 931 u8 conv_t1[ISP2X_DHAZ_CONV_COEFF_NUM]; 932 u8 conv_t2[ISP2X_DHAZ_CONV_COEFF_NUM]; 933} __attribute__((packed)); 934 935struct isp2x_dhaz_stat { 936 u16 dhaz_adp_air_base; 937 u16 dhaz_adp_wt; 938 939 u16 dhaz_adp_gratio; 940 u16 dhaz_adp_tmax; 941 942 u16 h_r_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 943 u16 h_g_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 944 u16 h_b_iir[ISP2X_DHAZ_HIST_IIR_NUM]; 945} __attribute__((packed)); 946 947struct isp2x_cproc_cfg { 948 u8 c_out_range; 949 u8 y_in_range; 950 u8 y_out_range; 951 u8 contrast; 952 u8 brightness; 953 u8 sat; 954 u8 hue; 955} __attribute__((packed)); 956 957struct isp2x_ie_cfg { 958 u16 effect; 959 u16 color_sel; 960 u16 eff_mat_1; 961 u16 eff_mat_2; 962 u16 eff_mat_3; 963 u16 eff_mat_4; 964 u16 eff_mat_5; 965 u16 eff_tint; 966} __attribute__((packed)); 967 968struct isp2x_rkiesharp_cfg { 969 u8 coring_thr; 970 u8 full_range; 971 u8 switch_avg; 972 u8 yavg_thr[4]; 973 u8 delta1[5]; 974 u8 delta2[5]; 975 u8 maxnumber[5]; 976 u8 minnumber[5]; 977 u8 gauss_flat_coe[9]; 978 u8 gauss_noise_coe[9]; 979 u8 gauss_other_coe[9]; 980 u8 line1_filter_coe[6]; 981 u8 line2_filter_coe[9]; 982 u8 line3_filter_coe[6]; 983 u16 grad_seq[4]; 984 u8 sharp_factor[5]; 985 u8 uv_gauss_flat_coe[15]; 986 u8 uv_gauss_noise_coe[15]; 987 u8 uv_gauss_other_coe[15]; 988 u8 lap_mat_coe[9]; 989} __attribute__((packed)); 990 991struct isp2x_superimp_cfg { 992 u8 transparency_mode; 993 u8 ref_image; 994 995 u16 offset_x; 996 u16 offset_y; 997 998 u8 y_comp; 999 u8 cb_comp; 1000 u8 cr_comp; 1001} __attribute__((packed)); 1002 1003struct isp2x_gamma_corr_curve { 1004 u16 gamma_y[ISP2X_DEGAMMA_CURVE_SIZE]; 1005} __attribute__((packed)); 1006 1007struct isp2x_gamma_curve_x_axis_pnts { 1008 u32 gamma_dx0; 1009 u32 gamma_dx1; 1010} __attribute__((packed)); 1011 1012struct isp2x_sdg_cfg { 1013 struct isp2x_gamma_corr_curve curve_r; 1014 struct isp2x_gamma_corr_curve curve_g; 1015 struct isp2x_gamma_corr_curve curve_b; 1016 struct isp2x_gamma_curve_x_axis_pnts xa_pnts; 1017} __attribute__((packed)); 1018 1019struct isp2x_bdm_config { 1020 unsigned char demosaic_th; 1021} __attribute__((packed)); 1022 1023struct isp2x_gain_cfg { 1024 u8 dhaz_en; 1025 u8 wdr_en; 1026 u8 tmo_en; 1027 u8 lsc_en; 1028 u8 mge_en; 1029 1030 u32 mge_gain[ISP2X_GAIN_HDRMGE_GAIN_NUM]; 1031 u16 idx[ISP2X_GAIN_IDX_NUM]; 1032 u16 lut[ISP2X_GAIN_LUT_NUM]; 1033} __attribute__((packed)); 1034 1035struct isp2x_3dlut_cfg { 1036 u8 bypass_en; 1037 u32 actual_size; // word unit 1038 u16 lut_r[ISP2X_3DLUT_DATA_NUM]; 1039 u16 lut_g[ISP2X_3DLUT_DATA_NUM]; 1040 u16 lut_b[ISP2X_3DLUT_DATA_NUM]; 1041} __attribute__((packed)); 1042 1043enum isp2x_ldch_buf_stat { 1044 LDCH_BUF_INIT = 0, 1045 LDCH_BUF_WAIT2CHIP, 1046 LDCH_BUF_CHIPINUSE, 1047}; 1048 1049struct rkisp_ldchbuf_info { 1050 s32 buf_fd[ISP2X_LDCH_BUF_NUM]; 1051 u32 buf_size[ISP2X_LDCH_BUF_NUM]; 1052} __attribute__((packed)); 1053 1054struct rkisp_ldchbuf_size { 1055 u32 meas_width; 1056 u32 meas_height; 1057} __attribute__((packed)); 1058 1059struct isp2x_ldch_head { 1060 enum isp2x_ldch_buf_stat stat; 1061 u32 data_oft; 1062} __attribute__((packed)); 1063 1064struct isp2x_ldch_cfg { 1065 u32 hsize; 1066 u32 vsize; 1067 s32 buf_fd; 1068} __attribute__((packed)); 1069 1070struct isp2x_awb_gain_cfg { 1071 u16 gain_red; 1072 u16 gain_green_r; 1073 u16 gain_blue; 1074 u16 gain_green_b; 1075} __attribute__((packed)); 1076 1077struct isp2x_siawb_meas_cfg { 1078 struct isp2x_window awb_wnd; 1079 u8 awb_mode; 1080 u8 max_y; 1081 u8 min_y; 1082 u8 max_csum; 1083 u8 min_c; 1084 u8 frames; 1085 u8 awb_ref_cr; 1086 u8 awb_ref_cb; 1087 u8 enable_ymax_cmp; 1088} __attribute__((packed)); 1089 1090struct isp2x_rawawb_meas_cfg { 1091 u8 rawawb_sel; 1092 u8 sw_rawawb_light_num; // CTRL 1093 u8 sw_rawawb_wind_size; // CTRL 1094 u8 sw_rawawb_c_range; // CTRL 1095 u8 sw_rawawb_y_range; // CTRL 1096 u8 sw_rawawb_3dyuv_ls_idx3; // CTRL 1097 u8 sw_rawawb_3dyuv_ls_idx2; // CTRL 1098 u8 sw_rawawb_3dyuv_ls_idx1; // CTRL 1099 u8 sw_rawawb_3dyuv_ls_idx0; // CTRL 1100 u8 sw_rawawb_xy_en; // CTRL 1101 u8 sw_rawawb_uv_en; // CTRL 1102 u8 sw_rawlsc_bypass_en; // CTRL 1103 u8 sw_rawawb_blk_measure_mode; // BLK_CTRL 1104 u8 sw_rawawb_store_wp_flag_ls_idx2; // BLK_CTRL 1105 u8 sw_rawawb_store_wp_flag_ls_idx1; // BLK_CTRL 1106 u8 sw_rawawb_store_wp_flag_ls_idx0; // BLK_CTRL 1107 u16 sw_rawawb_store_wp_th0; // BLK_CTRL 1108 u16 sw_rawawb_store_wp_th1; // BLK_CTRL 1109 u16 sw_rawawb_store_wp_th2; // RAW_CTRL 1110 u16 sw_rawawb_v_offs; // WIN_OFFS 1111 u16 sw_rawawb_h_offs; // WIN_OFFS 1112 u16 sw_rawawb_v_size; // WIN_SIZE 1113 u16 sw_rawawb_h_size; // WIN_SIZE 1114 u16 sw_rawawb_g_max; // LIMIT_RG_MAX 1115 u16 sw_rawawb_r_max; // LIMIT_RG_MAX 1116 u16 sw_rawawb_y_max; // LIMIT_BY_MAX 1117 u16 sw_rawawb_b_max; // LIMIT_BY_MAX 1118 u16 sw_rawawb_g_min; // LIMIT_RG_MIN 1119 u16 sw_rawawb_r_min; // LIMIT_RG_MIN 1120 u16 sw_rawawb_y_min; // LIMIT_BY_MIN 1121 u16 sw_rawawb_b_min; // LIMIT_BY_MIN 1122 u16 sw_rawawb_coeff_y_g; // RGB2Y_0 1123 u16 sw_rawawb_coeff_y_r; // RGB2Y_0 1124 u16 sw_rawawb_coeff_y_b; // RGB2Y_1 1125 u16 sw_rawawb_coeff_u_g; // RGB2U_0 1126 u16 sw_rawawb_coeff_u_r; // RGB2U_0 1127 u16 sw_rawawb_coeff_u_b; // RGB2U_1 1128 u16 sw_rawawb_coeff_v_g; // RGB2V_0 1129 u16 sw_rawawb_coeff_v_r; // RGB2V_0 1130 u16 sw_rawawb_coeff_v_b; // RGB2V_1 1131 u16 sw_rawawb_vertex0_v_0; // UV_DETC_VERTEX0_0 1132 u16 sw_rawawb_vertex0_u_0; // UV_DETC_VERTEX0_0 1133 u16 sw_rawawb_vertex1_v_0; // UV_DETC_VERTEX1_0 1134 u16 sw_rawawb_vertex1_u_0; // UV_DETC_VERTEX1_0 1135 u16 sw_rawawb_vertex2_v_0; // UV_DETC_VERTEX2_0 1136 u16 sw_rawawb_vertex2_u_0; // UV_DETC_VERTEX2_0 1137 u16 sw_rawawb_vertex3_v_0; // UV_DETC_VERTEX3_0 1138 u16 sw_rawawb_vertex3_u_0; // UV_DETC_VERTEX3_0 1139 u32 sw_rawawb_islope01_0; // UV_DETC_ISLOPE01_0 1140 u32 sw_rawawb_islope12_0; // UV_DETC_ISLOPE12_0 1141 u32 sw_rawawb_islope23_0; // UV_DETC_ISLOPE23_0 1142 u32 sw_rawawb_islope30_0; // UV_DETC_ISLOPE30_0 1143 u16 sw_rawawb_vertex0_v_1; // UV_DETC_VERTEX0_1 1144 u16 sw_rawawb_vertex0_u_1; // UV_DETC_VERTEX0_1 1145 u16 sw_rawawb_vertex1_v_1; // UV_DETC_VERTEX1_1 1146 u16 sw_rawawb_vertex1_u_1; // UV_DETC_VERTEX1_1 1147 u16 sw_rawawb_vertex2_v_1; // UV_DETC_VERTEX2_1 1148 u16 sw_rawawb_vertex2_u_1; // UV_DETC_VERTEX2_1 1149 u16 sw_rawawb_vertex3_v_1; // UV_DETC_VERTEX3_1 1150 u16 sw_rawawb_vertex3_u_1; // UV_DETC_VERTEX3_1 1151 u32 sw_rawawb_islope01_1; // UV_DETC_ISLOPE01_1 1152 u32 sw_rawawb_islope12_1; // UV_DETC_ISLOPE12_1 1153 u32 sw_rawawb_islope23_1; // UV_DETC_ISLOPE23_1 1154 u32 sw_rawawb_islope30_1; // UV_DETC_ISLOPE30_1 1155 u16 sw_rawawb_vertex0_v_2; // UV_DETC_VERTEX0_2 1156 u16 sw_rawawb_vertex0_u_2; // UV_DETC_VERTEX0_2 1157 u16 sw_rawawb_vertex1_v_2; // UV_DETC_VERTEX1_2 1158 u16 sw_rawawb_vertex1_u_2; // UV_DETC_VERTEX1_2 1159 u16 sw_rawawb_vertex2_v_2; // UV_DETC_VERTEX2_2 1160 u16 sw_rawawb_vertex2_u_2; // UV_DETC_VERTEX2_2 1161 u16 sw_rawawb_vertex3_v_2; // UV_DETC_VERTEX3_2 1162 u16 sw_rawawb_vertex3_u_2; // UV_DETC_VERTEX3_2 1163 u32 sw_rawawb_islope01_2; // UV_DETC_ISLOPE01_2 1164 u32 sw_rawawb_islope12_2; // UV_DETC_ISLOPE12_2 1165 u32 sw_rawawb_islope23_2; // UV_DETC_ISLOPE23_2 1166 u32 sw_rawawb_islope30_2; // UV_DETC_ISLOPE30_2 1167 u16 sw_rawawb_vertex0_v_3; // UV_DETC_VERTEX0_3 1168 u16 sw_rawawb_vertex0_u_3; // UV_DETC_VERTEX0_3 1169 u16 sw_rawawb_vertex1_v_3; // UV_DETC_VERTEX1_3 1170 u16 sw_rawawb_vertex1_u_3; // UV_DETC_VERTEX1_3 1171 u16 sw_rawawb_vertex2_v_3; // UV_DETC_VERTEX2_3 1172 u16 sw_rawawb_vertex2_u_3; // UV_DETC_VERTEX2_3 1173 u16 sw_rawawb_vertex3_v_3; // UV_DETC_VERTEX3_3 1174 u16 sw_rawawb_vertex3_u_3; // UV_DETC_VERTEX3_3 1175 u32 sw_rawawb_islope01_3; // UV_DETC_ISLOPE01_3 1176 u32 sw_rawawb_islope12_3; // UV_DETC_ISLOPE12_3 1177 u32 sw_rawawb_islope23_3; // UV_DETC_ISLOPE23_3 1178 u32 sw_rawawb_islope30_3; // UV_DETC_ISLOPE30_3 1179 u16 sw_rawawb_vertex0_v_4; // UV_DETC_VERTEX0_4 1180 u16 sw_rawawb_vertex0_u_4; // UV_DETC_VERTEX0_4 1181 u16 sw_rawawb_vertex1_v_4; // UV_DETC_VERTEX1_4 1182 u16 sw_rawawb_vertex1_u_4; // UV_DETC_VERTEX1_4 1183 u16 sw_rawawb_vertex2_v_4; // UV_DETC_VERTEX2_4 1184 u16 sw_rawawb_vertex2_u_4; // UV_DETC_VERTEX2_4 1185 u16 sw_rawawb_vertex3_v_4; // UV_DETC_VERTEX3_4 1186 u16 sw_rawawb_vertex3_u_4; // UV_DETC_VERTEX3_4 1187 u32 sw_rawawb_islope01_4; // UV_DETC_ISLOPE01_4 1188 u32 sw_rawawb_islope12_4; // UV_DETC_ISLOPE12_4 1189 u32 sw_rawawb_islope23_4; // UV_DETC_ISLOPE23_4 1190 u32 sw_rawawb_islope30_4; // UV_DETC_ISLOPE30_4 1191 u16 sw_rawawb_vertex0_v_5; // UV_DETC_VERTEX0_5 1192 u16 sw_rawawb_vertex0_u_5; // UV_DETC_VERTEX0_5 1193 u16 sw_rawawb_vertex1_v_5; // UV_DETC_VERTEX1_5 1194 u16 sw_rawawb_vertex1_u_5; // UV_DETC_VERTEX1_5 1195 u16 sw_rawawb_vertex2_v_5; // UV_DETC_VERTEX2_5 1196 u16 sw_rawawb_vertex2_u_5; // UV_DETC_VERTEX2_5 1197 u16 sw_rawawb_vertex3_v_5; // UV_DETC_VERTEX3_5 1198 u16 sw_rawawb_vertex3_u_5; // UV_DETC_VERTEX3_5 1199 u32 sw_rawawb_islope01_5; // UV_DETC_ISLOPE01_5 1200 u32 sw_rawawb_islope12_5; // UV_DETC_ISLOPE10_5 1201 u32 sw_rawawb_islope23_5; // UV_DETC_ISLOPE23_5 1202 u32 sw_rawawb_islope30_5; // UV_DETC_ISLOPE30_5 1203 u16 sw_rawawb_vertex0_v_6; // UV_DETC_VERTEX0_6 1204 u16 sw_rawawb_vertex0_u_6; // UV_DETC_VERTEX0_6 1205 u16 sw_rawawb_vertex1_v_6; // UV_DETC_VERTEX1_6 1206 u16 sw_rawawb_vertex1_u_6; // UV_DETC_VERTEX1_6 1207 u16 sw_rawawb_vertex2_v_6; // UV_DETC_VERTEX2_6 1208 u16 sw_rawawb_vertex2_u_6; // UV_DETC_VERTEX2_6 1209 u16 sw_rawawb_vertex3_v_6; // UV_DETC_VERTEX3_6 1210 u16 sw_rawawb_vertex3_u_6; // UV_DETC_VERTEX3_6 1211 u32 sw_rawawb_islope01_6; // UV_DETC_ISLOPE01_6 1212 u32 sw_rawawb_islope12_6; // UV_DETC_ISLOPE10_6 1213 u32 sw_rawawb_islope23_6; // UV_DETC_ISLOPE23_6 1214 u32 sw_rawawb_islope30_6; // UV_DETC_ISLOPE30_6 1215 u32 sw_rawawb_b_uv_0; // YUV_DETC_B_UV_0 1216 u32 sw_rawawb_slope_vtcuv_0; // YUV_DETC_SLOPE_VTCUV_0 1217 u32 sw_rawawb_inv_dslope_0; // YUV_DETC_INV_DSLOPE_0 1218 u32 sw_rawawb_slope_ydis_0; // YUV_DETC_SLOPE_YDIS_0 1219 u32 sw_rawawb_b_ydis_0; // YUV_DETC_B_YDIS_0 1220 u32 sw_rawawb_b_uv_1; // YUV_DETC_B_UV_1 1221 u32 sw_rawawb_slope_vtcuv_1; // YUV_DETC_SLOPE_VTCUV_1 1222 u32 sw_rawawb_inv_dslope_1; // YUV_DETC_INV_DSLOPE_1 1223 u32 sw_rawawb_slope_ydis_1; // YUV_DETC_SLOPE_YDIS_1 1224 u32 sw_rawawb_b_ydis_1; // YUV_DETC_B_YDIS_1 1225 u32 sw_rawawb_b_uv_2; // YUV_DETC_B_UV_2 1226 u32 sw_rawawb_slope_vtcuv_2; // YUV_DETC_SLOPE_VTCUV_2 1227 u32 sw_rawawb_inv_dslope_2; // YUV_DETC_INV_DSLOPE_2 1228 u32 sw_rawawb_slope_ydis_2; // YUV_DETC_SLOPE_YDIS_2 1229 u32 sw_rawawb_b_ydis_2; // YUV_DETC_B_YDIS_2 1230 u32 sw_rawawb_b_uv_3; // YUV_DETC_B_UV_3 1231 u32 sw_rawawb_slope_vtcuv_3; // YUV_DETC_SLOPE_VTCUV_3 1232 u32 sw_rawawb_inv_dslope_3; // YUV_DETC_INV_DSLOPE_3 1233 u32 sw_rawawb_slope_ydis_3; // YUV_DETC_SLOPE_YDIS_3 1234 u32 sw_rawawb_b_ydis_3; // YUV_DETC_B_YDIS_3 1235 u32 sw_rawawb_ref_u; // YUV_DETC_REF_U 1236 u8 sw_rawawb_ref_v_3; // YUV_DETC_REF_V_1 1237 u8 sw_rawawb_ref_v_2; // YUV_DETC_REF_V_1 1238 u8 sw_rawawb_ref_v_1; // YUV_DETC_REF_V_1 1239 u8 sw_rawawb_ref_v_0; // YUV_DETC_REF_V_1 1240 u16 sw_rawawb_dis1_0; // YUV_DETC_DIS01_0 1241 u16 sw_rawawb_dis0_0; // YUV_DETC_DIS01_0 1242 u16 sw_rawawb_dis3_0; // YUV_DETC_DIS23_0 1243 u16 sw_rawawb_dis2_0; // YUV_DETC_DIS23_0 1244 u16 sw_rawawb_dis5_0; // YUV_DETC_DIS45_0 1245 u16 sw_rawawb_dis4_0; // YUV_DETC_DIS45_0 1246 u8 sw_rawawb_th3_0; // YUV_DETC_TH03_0 1247 u8 sw_rawawb_th2_0; // YUV_DETC_TH03_0 1248 u8 sw_rawawb_th1_0; // YUV_DETC_TH03_0 1249 u8 sw_rawawb_th0_0; // YUV_DETC_TH03_0 1250 u8 sw_rawawb_th5_0; // YUV_DETC_TH45_0 1251 u8 sw_rawawb_th4_0; // YUV_DETC_TH45_0 1252 u16 sw_rawawb_dis1_1; // YUV_DETC_DIS01_1 1253 u16 sw_rawawb_dis0_1; // YUV_DETC_DIS01_1 1254 u16 sw_rawawb_dis3_1; // YUV_DETC_DIS23_1 1255 u16 sw_rawawb_dis2_1; // YUV_DETC_DIS23_1 1256 u16 sw_rawawb_dis5_1; // YUV_DETC_DIS45_1 1257 u16 sw_rawawb_dis4_1; // YUV_DETC_DIS45_1 1258 u8 sw_rawawb_th3_1; // YUV_DETC_TH03_1 1259 u8 sw_rawawb_th2_1; // YUV_DETC_TH03_1 1260 u8 sw_rawawb_th1_1; // YUV_DETC_TH03_1 1261 u8 sw_rawawb_th0_1; // YUV_DETC_TH03_1 1262 u8 sw_rawawb_th5_1; // YUV_DETC_TH45_1 1263 u8 sw_rawawb_th4_1; // YUV_DETC_TH45_1 1264 u16 sw_rawawb_dis1_2; // YUV_DETC_DIS01_2 1265 u16 sw_rawawb_dis0_2; // YUV_DETC_DIS01_2 1266 u16 sw_rawawb_dis3_2; // YUV_DETC_DIS23_2 1267 u16 sw_rawawb_dis2_2; // YUV_DETC_DIS23_2 1268 u16 sw_rawawb_dis5_2; // YUV_DETC_DIS45_2 1269 u16 sw_rawawb_dis4_2; // YUV_DETC_DIS45_2 1270 u8 sw_rawawb_th3_2; // YUV_DETC_TH03_2 1271 u8 sw_rawawb_th2_2; // YUV_DETC_TH03_2 1272 u8 sw_rawawb_th1_2; // YUV_DETC_TH03_2 1273 u8 sw_rawawb_th0_2; // YUV_DETC_TH03_2 1274 u8 sw_rawawb_th5_2; // YUV_DETC_TH45_2 1275 u8 sw_rawawb_th4_2; // YUV_DETC_TH45_2 1276 u16 sw_rawawb_dis1_3; // YUV_DETC_DIS01_3 1277 u16 sw_rawawb_dis0_3; // YUV_DETC_DIS01_3 1278 u16 sw_rawawb_dis3_3; // YUV_DETC_DIS23_3 1279 u16 sw_rawawb_dis2_3; // YUV_DETC_DIS23_3 1280 u16 sw_rawawb_dis5_3; // YUV_DETC_DIS45_3 1281 u16 sw_rawawb_dis4_3; // YUV_DETC_DIS45_3 1282 u8 sw_rawawb_th3_3; // YUV_DETC_TH03_3 1283 u8 sw_rawawb_th2_3; // YUV_DETC_TH03_3 1284 u8 sw_rawawb_th1_3; // YUV_DETC_TH03_3 1285 u8 sw_rawawb_th0_3; // YUV_DETC_TH03_3 1286 u8 sw_rawawb_th5_3; // YUV_DETC_TH45_3 1287 u8 sw_rawawb_th4_3; // YUV_DETC_TH45_3 1288 u16 sw_rawawb_wt1; // RGB2XY_WT01 1289 u16 sw_rawawb_wt0; // RGB2XY_WT01 1290 u16 sw_rawawb_wt2; // RGB2XY_WT2 1291 u16 sw_rawawb_mat0_y; // RGB2XY_MAT0_XY 1292 u16 sw_rawawb_mat0_x; // RGB2XY_MAT0_XY 1293 u16 sw_rawawb_mat1_y; // RGB2XY_MAT1_XY 1294 u16 sw_rawawb_mat1_x; // RGB2XY_MAT1_XY 1295 u16 sw_rawawb_mat2_y; // RGB2XY_MAT2_XY 1296 u16 sw_rawawb_mat2_x; // RGB2XY_MAT2_XY 1297 u16 sw_rawawb_nor_x1_0; // XY_DETC_NOR_X_0 1298 u16 sw_rawawb_nor_x0_0; // XY_DETC_NOR_X_0 1299 u16 sw_rawawb_nor_y1_0; // XY_DETC_NOR_Y_0 1300 u16 sw_rawawb_nor_y0_0; // XY_DETC_NOR_Y_0 1301 u16 sw_rawawb_big_x1_0; // XY_DETC_BIG_X_0 1302 u16 sw_rawawb_big_x0_0; // XY_DETC_BIG_X_0 1303 u16 sw_rawawb_big_y1_0; // XY_DETC_BIG_Y_0 1304 u16 sw_rawawb_big_y0_0; // XY_DETC_BIG_Y_0 1305 u16 sw_rawawb_sma_x1_0; // XY_DETC_SMA_X_0 1306 u16 sw_rawawb_sma_x0_0; // XY_DETC_SMA_X_0 1307 u16 sw_rawawb_sma_y1_0; // XY_DETC_SMA_Y_0 1308 u16 sw_rawawb_sma_y0_0; // XY_DETC_SMA_Y_0 1309 u16 sw_rawawb_nor_x1_1; // XY_DETC_NOR_X_1 1310 u16 sw_rawawb_nor_x0_1; // XY_DETC_NOR_X_1 1311 u16 sw_rawawb_nor_y1_1; // XY_DETC_NOR_Y_1 1312 u16 sw_rawawb_nor_y0_1; // XY_DETC_NOR_Y_1 1313 u16 sw_rawawb_big_x1_1; // XY_DETC_BIG_X_1 1314 u16 sw_rawawb_big_x0_1; // XY_DETC_BIG_X_1 1315 u16 sw_rawawb_big_y1_1; // XY_DETC_BIG_Y_1 1316 u16 sw_rawawb_big_y0_1; // XY_DETC_BIG_Y_1 1317 u16 sw_rawawb_sma_x1_1; // XY_DETC_SMA_X_1 1318 u16 sw_rawawb_sma_x0_1; // XY_DETC_SMA_X_1 1319 u16 sw_rawawb_sma_y1_1; // XY_DETC_SMA_Y_1 1320 u16 sw_rawawb_sma_y0_1; // XY_DETC_SMA_Y_1 1321 u16 sw_rawawb_nor_x1_2; // XY_DETC_NOR_X_2 1322 u16 sw_rawawb_nor_x0_2; // XY_DETC_NOR_X_2 1323 u16 sw_rawawb_nor_y1_2; // XY_DETC_NOR_Y_2 1324 u16 sw_rawawb_nor_y0_2; // XY_DETC_NOR_Y_2 1325 u16 sw_rawawb_big_x1_2; // XY_DETC_BIG_X_2 1326 u16 sw_rawawb_big_x0_2; // XY_DETC_BIG_X_2 1327 u16 sw_rawawb_big_y1_2; // XY_DETC_BIG_Y_2 1328 u16 sw_rawawb_big_y0_2; // XY_DETC_BIG_Y_2 1329 u16 sw_rawawb_sma_x1_2; // XY_DETC_SMA_X_2 1330 u16 sw_rawawb_sma_x0_2; // XY_DETC_SMA_X_2 1331 u16 sw_rawawb_sma_y1_2; // XY_DETC_SMA_Y_2 1332 u16 sw_rawawb_sma_y0_2; // XY_DETC_SMA_Y_2 1333 u16 sw_rawawb_nor_x1_3; // XY_DETC_NOR_X_3 1334 u16 sw_rawawb_nor_x0_3; // XY_DETC_NOR_X_3 1335 u16 sw_rawawb_nor_y1_3; // XY_DETC_NOR_Y_3 1336 u16 sw_rawawb_nor_y0_3; // XY_DETC_NOR_Y_3 1337 u16 sw_rawawb_big_x1_3; // XY_DETC_BIG_X_3 1338 u16 sw_rawawb_big_x0_3; // XY_DETC_BIG_X_3 1339 u16 sw_rawawb_big_y1_3; // XY_DETC_BIG_Y_3 1340 u16 sw_rawawb_big_y0_3; // XY_DETC_BIG_Y_3 1341 u16 sw_rawawb_sma_x1_3; // XY_DETC_SMA_X_3 1342 u16 sw_rawawb_sma_x0_3; // XY_DETC_SMA_X_3 1343 u16 sw_rawawb_sma_y1_3; // XY_DETC_SMA_Y_3 1344 u16 sw_rawawb_sma_y0_3; // XY_DETC_SMA_Y_3 1345 u16 sw_rawawb_nor_x1_4; // XY_DETC_NOR_X_4 1346 u16 sw_rawawb_nor_x0_4; // XY_DETC_NOR_X_4 1347 u16 sw_rawawb_nor_y1_4; // XY_DETC_NOR_Y_4 1348 u16 sw_rawawb_nor_y0_4; // XY_DETC_NOR_Y_4 1349 u16 sw_rawawb_big_x1_4; // XY_DETC_BIG_X_4 1350 u16 sw_rawawb_big_x0_4; // XY_DETC_BIG_X_4 1351 u16 sw_rawawb_big_y1_4; // XY_DETC_BIG_Y_4 1352 u16 sw_rawawb_big_y0_4; // XY_DETC_BIG_Y_4 1353 u16 sw_rawawb_sma_x1_4; // XY_DETC_SMA_X_4 1354 u16 sw_rawawb_sma_x0_4; // XY_DETC_SMA_X_4 1355 u16 sw_rawawb_sma_y1_4; // XY_DETC_SMA_Y_4 1356 u16 sw_rawawb_sma_y0_4; // XY_DETC_SMA_Y_4 1357 u16 sw_rawawb_nor_x1_5; // XY_DETC_NOR_X_5 1358 u16 sw_rawawb_nor_x0_5; // XY_DETC_NOR_X_5 1359 u16 sw_rawawb_nor_y1_5; // XY_DETC_NOR_Y_5 1360 u16 sw_rawawb_nor_y0_5; // XY_DETC_NOR_Y_5 1361 u16 sw_rawawb_big_x1_5; // XY_DETC_BIG_X_5 1362 u16 sw_rawawb_big_x0_5; // XY_DETC_BIG_X_5 1363 u16 sw_rawawb_big_y1_5; // XY_DETC_BIG_Y_5 1364 u16 sw_rawawb_big_y0_5; // XY_DETC_BIG_Y_5 1365 u16 sw_rawawb_sma_x1_5; // XY_DETC_SMA_X_5 1366 u16 sw_rawawb_sma_x0_5; // XY_DETC_SMA_X_5 1367 u16 sw_rawawb_sma_y1_5; // XY_DETC_SMA_Y_5 1368 u16 sw_rawawb_sma_y0_5; // XY_DETC_SMA_Y_5 1369 u16 sw_rawawb_nor_x1_6; // XY_DETC_NOR_X_6 1370 u16 sw_rawawb_nor_x0_6; // XY_DETC_NOR_X_6 1371 u16 sw_rawawb_nor_y1_6; // XY_DETC_NOR_Y_6 1372 u16 sw_rawawb_nor_y0_6; // XY_DETC_NOR_Y_6 1373 u16 sw_rawawb_big_x1_6; // XY_DETC_BIG_X_6 1374 u16 sw_rawawb_big_x0_6; // XY_DETC_BIG_X_6 1375 u16 sw_rawawb_big_y1_6; // XY_DETC_BIG_Y_6 1376 u16 sw_rawawb_big_y0_6; // XY_DETC_BIG_Y_6 1377 u16 sw_rawawb_sma_x1_6; // XY_DETC_SMA_X_6 1378 u16 sw_rawawb_sma_x0_6; // XY_DETC_SMA_X_6 1379 u16 sw_rawawb_sma_y1_6; // XY_DETC_SMA_Y_6 1380 u16 sw_rawawb_sma_y0_6; // XY_DETC_SMA_Y_6 1381 u8 sw_rawawb_multiwindow_en; // MULTIWINDOW_EXC_CTRL 1382 u8 sw_rawawb_exc_wp_region6_domain; // MULTIWINDOW_EXC_CTRL 1383 u8 sw_rawawb_exc_wp_region6_measen; // MULTIWINDOW_EXC_CTRL 1384 u8 sw_rawawb_exc_wp_region6_excen; // MULTIWINDOW_EXC_CTRL 1385 u8 sw_rawawb_exc_wp_region5_domain; // MULTIWINDOW_EXC_CTRL 1386 u8 sw_rawawb_exc_wp_region5_measen; // MULTIWINDOW_EXC_CTRL 1387 u8 sw_rawawb_exc_wp_region5_excen; // MULTIWINDOW_EXC_CTRL 1388 u8 sw_rawawb_exc_wp_region4_domain; // MULTIWINDOW_EXC_CTRL 1389 u8 sw_rawawb_exc_wp_region4_measen; // MULTIWINDOW_EXC_CTRL 1390 u8 sw_rawawb_exc_wp_region4_excen; // MULTIWINDOW_EXC_CTRL 1391 u8 sw_rawawb_exc_wp_region3_domain; // MULTIWINDOW_EXC_CTRL 1392 u8 sw_rawawb_exc_wp_region3_measen; // MULTIWINDOW_EXC_CTRL 1393 u8 sw_rawawb_exc_wp_region3_excen; // MULTIWINDOW_EXC_CTRL 1394 u8 sw_rawawb_exc_wp_region2_domain; // MULTIWINDOW_EXC_CTRL 1395 u8 sw_rawawb_exc_wp_region2_measen; // MULTIWINDOW_EXC_CTRL 1396 u8 sw_rawawb_exc_wp_region2_excen; // MULTIWINDOW_EXC_CTRL 1397 u8 sw_rawawb_exc_wp_region1_domain; // MULTIWINDOW_EXC_CTRL 1398 u8 sw_rawawb_exc_wp_region1_measen; // MULTIWINDOW_EXC_CTRL 1399 u8 sw_rawawb_exc_wp_region1_excen; // MULTIWINDOW_EXC_CTRL 1400 u8 sw_rawawb_exc_wp_region0_domain; // MULTIWINDOW_EXC_CTRL 1401 u8 sw_rawawb_exc_wp_region0_measen; // MULTIWINDOW_EXC_CTRL 1402 u8 sw_rawawb_exc_wp_region0_excen; // MULTIWINDOW_EXC_CTRL 1403 u16 sw_rawawb_multiwindow0_v_offs; // MULTIWINDOW0_OFFS 1404 u16 sw_rawawb_multiwindow0_h_offs; // MULTIWINDOW0_OFFS 1405 u16 sw_rawawb_multiwindow0_v_size; // MULTIWINDOW0_SIZE 1406 u16 sw_rawawb_multiwindow0_h_size; // MULTIWINDOW0_SIZE 1407 u16 sw_rawawb_multiwindow1_v_offs; // MULTIWINDOW1_OFFS 1408 u16 sw_rawawb_multiwindow1_h_offs; // MULTIWINDOW1_OFFS 1409 u16 sw_rawawb_multiwindow1_v_size; // MULTIWINDOW1_SIZE 1410 u16 sw_rawawb_multiwindow1_h_size; // MULTIWINDOW1_SIZE 1411 u16 sw_rawawb_multiwindow2_v_offs; // MULTIWINDOW2_OFFS 1412 u16 sw_rawawb_multiwindow2_h_offs; // MULTIWINDOW2_OFFS 1413 u16 sw_rawawb_multiwindow2_v_size; // MULTIWINDOW2_SIZE 1414 u16 sw_rawawb_multiwindow2_h_size; // MULTIWINDOW2_SIZE 1415 u16 sw_rawawb_multiwindow3_v_offs; // MULTIWINDOW3_OFFS 1416 u16 sw_rawawb_multiwindow3_h_offs; // MULTIWINDOW3_OFFS 1417 u16 sw_rawawb_multiwindow3_v_size; // MULTIWINDOW3_SIZE 1418 u16 sw_rawawb_multiwindow3_h_size; // MULTIWINDOW3_SIZE 1419 u16 sw_rawawb_multiwindow4_v_offs; // MULTIWINDOW4_OFFS 1420 u16 sw_rawawb_multiwindow4_h_offs; // MULTIWINDOW4_OFFS 1421 u16 sw_rawawb_multiwindow4_v_size; // MULTIWINDOW4_SIZE 1422 u16 sw_rawawb_multiwindow4_h_size; // MULTIWINDOW4_SIZE 1423 u16 sw_rawawb_multiwindow5_v_offs; // MULTIWINDOW5_OFFS 1424 u16 sw_rawawb_multiwindow5_h_offs; // MULTIWINDOW5_OFFS 1425 u16 sw_rawawb_multiwindow5_v_size; // MULTIWINDOW5_SIZE 1426 u16 sw_rawawb_multiwindow5_h_size; // MULTIWINDOW5_SIZE 1427 u16 sw_rawawb_multiwindow6_v_offs; // MULTIWINDOW6_OFFS 1428 u16 sw_rawawb_multiwindow6_h_offs; // MULTIWINDOW6_OFFS 1429 u16 sw_rawawb_multiwindow6_v_size; // MULTIWINDOW6_SIZE 1430 u16 sw_rawawb_multiwindow6_h_size; // MULTIWINDOW6_SIZE 1431 u16 sw_rawawb_multiwindow7_v_offs; // MULTIWINDOW7_OFFS 1432 u16 sw_rawawb_multiwindow7_h_offs; // MULTIWINDOW7_OFFS 1433 u16 sw_rawawb_multiwindow7_v_size; // MULTIWINDOW7_SIZE 1434 u16 sw_rawawb_multiwindow7_h_size; // MULTIWINDOW7_SIZE 1435 u16 sw_rawawb_exc_wp_region0_xu1; // EXC_WP_REGION0_XU 1436 u16 sw_rawawb_exc_wp_region0_xu0; // EXC_WP_REGION0_XU 1437 u16 sw_rawawb_exc_wp_region0_yv1; // EXC_WP_REGION0_YV 1438 u16 sw_rawawb_exc_wp_region0_yv0; // EXC_WP_REGION0_YV 1439 u16 sw_rawawb_exc_wp_region1_xu1; // EXC_WP_REGION1_XU 1440 u16 sw_rawawb_exc_wp_region1_xu0; // EXC_WP_REGION1_XU 1441 u16 sw_rawawb_exc_wp_region1_yv1; // EXC_WP_REGION1_YV 1442 u16 sw_rawawb_exc_wp_region1_yv0; // EXC_WP_REGION1_YV 1443 u16 sw_rawawb_exc_wp_region2_xu1; // EXC_WP_REGION2_XU 1444 u16 sw_rawawb_exc_wp_region2_xu0; // EXC_WP_REGION2_XU 1445 u16 sw_rawawb_exc_wp_region2_yv1; // EXC_WP_REGION2_YV 1446 u16 sw_rawawb_exc_wp_region2_yv0; // EXC_WP_REGION2_YV 1447 u16 sw_rawawb_exc_wp_region3_xu1; // EXC_WP_REGION3_XU 1448 u16 sw_rawawb_exc_wp_region3_xu0; // EXC_WP_REGION3_XU 1449 u16 sw_rawawb_exc_wp_region3_yv1; // EXC_WP_REGION3_YV 1450 u16 sw_rawawb_exc_wp_region3_yv0; // EXC_WP_REGION3_YV 1451 u16 sw_rawawb_exc_wp_region4_xu1; // EXC_WP_REGION4_XU 1452 u16 sw_rawawb_exc_wp_region4_xu0; // EXC_WP_REGION4_XU 1453 u16 sw_rawawb_exc_wp_region4_yv1; // EXC_WP_REGION4_YV 1454 u16 sw_rawawb_exc_wp_region4_yv0; // EXC_WP_REGION4_YV 1455 u16 sw_rawawb_exc_wp_region5_xu1; // EXC_WP_REGION5_XU 1456 u16 sw_rawawb_exc_wp_region5_xu0; // EXC_WP_REGION5_XU 1457 u16 sw_rawawb_exc_wp_region5_yv1; // EXC_WP_REGION5_YV 1458 u16 sw_rawawb_exc_wp_region5_yv0; // EXC_WP_REGION5_YV 1459 u16 sw_rawawb_exc_wp_region6_xu1; // EXC_WP_REGION6_XU 1460 u16 sw_rawawb_exc_wp_region6_xu0; // EXC_WP_REGION6_XU 1461 u16 sw_rawawb_exc_wp_region6_yv1; // EXC_WP_REGION6_YV 1462 u16 sw_rawawb_exc_wp_region6_yv0; // EXC_WP_REGION6_YV 1463} __attribute__((packed)); 1464 1465struct isp2x_rawaebig_meas_cfg { 1466 u8 rawae_sel; 1467 u8 wnd_num; 1468 u8 subwin_en[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1469 struct isp2x_window win; 1470 struct isp2x_window subwin[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1471} __attribute__((packed)); 1472 1473struct isp2x_rawaelite_meas_cfg { 1474 u8 rawae_sel; 1475 u8 wnd_num; 1476 struct isp2x_window win; 1477} __attribute__((packed)); 1478 1479struct isp2x_yuvae_meas_cfg { 1480 u8 ysel; 1481 u8 wnd_num; 1482 u8 subwin_en[ISP2X_YUVAE_SUBWIN_NUM]; 1483 struct isp2x_window win; 1484 struct isp2x_window subwin[ISP2X_YUVAE_SUBWIN_NUM]; 1485} __attribute__((packed)); 1486 1487struct isp2x_rawaf_meas_cfg { 1488 u8 rawaf_sel; 1489 u8 num_afm_win; 1490 u8 gaus_en; 1491 u8 gamma_en; 1492 struct isp2x_window win[ISP2X_RAWAF_WIN_NUM]; 1493 u8 line_en[ISP2X_RAWAF_LINE_NUM]; 1494 u8 line_num[ISP2X_RAWAF_LINE_NUM]; 1495 u8 gaus_coe_h2; 1496 u8 gaus_coe_h1; 1497 u8 gaus_coe_h0; 1498 u16 afm_thres; 1499 u8 lum_var_shift[ISP2X_RAWAF_WIN_NUM]; 1500 u8 afm_var_shift[ISP2X_RAWAF_WIN_NUM]; 1501 u16 gamma_y[ISP2X_RAWAF_GAMMA_NUM]; 1502} __attribute__((packed)); 1503 1504struct isp2x_siaf_win_cfg { 1505 u8 sum_shift; 1506 u8 lum_shift; 1507 struct isp2x_window win; 1508} __attribute__((packed)); 1509 1510struct isp2x_siaf_cfg { 1511 u8 num_afm_win; 1512 u32 thres; 1513 struct isp2x_siaf_win_cfg afm_win[ISP2X_AFM_MAX_WINDOWS]; 1514} __attribute__((packed)); 1515 1516struct isp2x_rawhistbig_cfg { 1517 u8 wnd_num; 1518 u8 data_sel; 1519 u8 waterline; 1520 u8 mode; 1521 u8 stepsize; 1522 u8 off; 1523 u8 bcc; 1524 u8 gcc; 1525 u8 rcc; 1526 struct isp2x_window win; 1527 u8 weight[ISP2X_RAWHISTBIG_SUBWIN_NUM]; 1528} __attribute__((packed)); 1529 1530struct isp2x_rawhistlite_cfg { 1531 u8 data_sel; 1532 u8 waterline; 1533 u8 mode; 1534 u8 stepsize; 1535 u8 off; 1536 u8 bcc; 1537 u8 gcc; 1538 u8 rcc; 1539 struct isp2x_window win; 1540 u8 weight[ISP2X_RAWHISTLITE_SUBWIN_NUM]; 1541} __attribute__((packed)); 1542 1543struct isp2x_sihst_win_cfg { 1544 u8 data_sel; 1545 u8 waterline; 1546 u8 auto_stop; 1547 u8 mode; 1548 u8 stepsize; 1549 struct isp2x_window win; 1550} __attribute__((packed)); 1551 1552struct isp2x_sihst_cfg { 1553 u8 wnd_num; 1554 struct isp2x_sihst_win_cfg win_cfg[ISP2X_SIHIST_WIN_NUM]; 1555 u8 hist_weight[ISP2X_HIST_WEIGHT_NUM]; 1556} __attribute__((packed)); 1557 1558struct isp2x_isp_other_cfg { 1559 struct isp2x_bls_cfg bls_cfg; 1560 struct isp2x_dpcc_cfg dpcc_cfg; 1561 struct isp2x_hdrmge_cfg hdrmge_cfg; 1562 struct isp2x_rawnr_cfg rawnr_cfg; 1563 struct isp2x_lsc_cfg lsc_cfg; 1564 struct isp2x_awb_gain_cfg awb_gain_cfg; 1565 struct isp2x_gic_cfg gic_cfg; 1566 struct isp2x_debayer_cfg debayer_cfg; 1567 struct isp2x_ccm_cfg ccm_cfg; 1568 struct isp2x_gammaout_cfg gammaout_cfg; 1569 struct isp2x_wdr_cfg wdr_cfg; 1570 struct isp2x_cproc_cfg cproc_cfg; 1571 struct isp2x_ie_cfg ie_cfg; 1572 struct isp2x_rkiesharp_cfg rkiesharp_cfg; 1573 struct isp2x_superimp_cfg superimp_cfg; 1574 struct isp2x_sdg_cfg sdg_cfg; 1575 struct isp2x_bdm_config bdm_cfg; 1576 struct isp2x_hdrtmo_cfg hdrtmo_cfg; 1577 struct isp2x_dhaz_cfg dhaz_cfg; 1578 struct isp2x_gain_cfg gain_cfg; 1579 struct isp2x_3dlut_cfg isp3dlut_cfg; 1580 struct isp2x_ldch_cfg ldch_cfg; 1581} __attribute__((packed)); 1582 1583struct isp2x_isp_meas_cfg { 1584 struct isp2x_siawb_meas_cfg siawb; 1585 struct isp2x_rawawb_meas_cfg rawawb; 1586 struct isp2x_rawaelite_meas_cfg rawae0; 1587 struct isp2x_rawaebig_meas_cfg rawae1; 1588 struct isp2x_rawaebig_meas_cfg rawae2; 1589 struct isp2x_rawaebig_meas_cfg rawae3; 1590 struct isp2x_yuvae_meas_cfg yuvae; 1591 struct isp2x_rawaf_meas_cfg rawaf; 1592 struct isp2x_siaf_cfg siaf; 1593 struct isp2x_rawhistlite_cfg rawhist0; 1594 struct isp2x_rawhistbig_cfg rawhist1; 1595 struct isp2x_rawhistbig_cfg rawhist2; 1596 struct isp2x_rawhistbig_cfg rawhist3; 1597 struct isp2x_sihst_cfg sihst; 1598} __attribute__((packed)); 1599 1600struct sensor_exposure_s { 1601 u32 fine_integration_time; 1602 u32 coarse_integration_time; 1603 u32 analog_gain_code_global; 1604 u32 digital_gain_global; 1605 u32 isp_digital_gain; 1606} __attribute__((packed)); 1607 1608struct sensor_exposure_cfg { 1609 struct sensor_exposure_s linear_exp; 1610 struct sensor_exposure_s hdr_exp[3]; 1611} __attribute__((packed)); 1612 1613struct isp2x_isp_params_cfg { 1614 u64 module_en_update; 1615 u64 module_ens; 1616 u64 module_cfg_update; 1617 1618 u32 frame_id; 1619 struct isp2x_isp_meas_cfg meas; 1620 struct isp2x_isp_other_cfg others; 1621 struct sensor_exposure_cfg exposure; 1622} __attribute__((packed)); 1623 1624struct isp2x_siawb_meas { 1625 u32 cnt; 1626 u8 mean_y_or_g; 1627 u8 mean_cb_or_b; 1628 u8 mean_cr_or_r; 1629} __attribute__((packed)); 1630 1631struct isp2x_siawb_stat { 1632 struct isp2x_siawb_meas awb_mean[ISP2X_AWB_MAX_GRID]; 1633} __attribute__((packed)); 1634 1635struct isp2x_rawawb_ramdata { 1636 u32 wp; 1637 u32 r; 1638 u32 g; 1639 u32 b; 1640}; 1641 1642struct isp2x_rawawb_meas_stat { 1643 u32 ro_rawawb_sum_r_nor[ISP2X_RAWAWB_SUM_NUM]; // SUM_R_NOR_0 1644 u32 ro_rawawb_sum_g_nor[ISP2X_RAWAWB_SUM_NUM]; // SUM_G_NOR_0 1645 u32 ro_rawawb_sum_b_nor[ISP2X_RAWAWB_SUM_NUM]; // SUM_B_NOR_0 1646 u32 ro_rawawb_wp_num_nor[ISP2X_RAWAWB_SUM_NUM]; // WP_NUM_NOR_0 1647 u32 ro_rawawb_sum_r_big[ISP2X_RAWAWB_SUM_NUM]; // SUM_R_BIG_0 1648 u32 ro_rawawb_sum_g_big[ISP2X_RAWAWB_SUM_NUM]; // SUM_G_BIG_0 1649 u32 ro_rawawb_sum_b_big[ISP2X_RAWAWB_SUM_NUM]; // SUM_B_BIG_0 1650 u32 ro_rawawb_wp_num_big[ISP2X_RAWAWB_SUM_NUM]; // WP_NUM_BIG_0 1651 u32 ro_rawawb_sum_r_sma[ISP2X_RAWAWB_SUM_NUM]; // SUM_R_SMA_0 1652 u32 ro_rawawb_sum_g_sma[ISP2X_RAWAWB_SUM_NUM]; // SUM_G_SMA_0 1653 u32 ro_rawawb_sum_b_sma[ISP2X_RAWAWB_SUM_NUM]; // SUM_B_SMA_0 1654 u32 ro_rawawb_wp_num_sma[ISP2X_RAWAWB_SUM_NUM]; 1655 u32 ro_sum_r_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_R_NOR_MULTIWINDOW_0 1656 u32 ro_sum_g_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_G_NOR_MULTIWINDOW_0 1657 u32 ro_sum_b_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_B_NOR_MULTIWINDOW_0 1658 u32 ro_wp_nm_nor_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // WP_NM_NOR_MULTIWINDOW_0 1659 u32 ro_sum_r_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_R_BIG_MULTIWINDOW_0 1660 u32 ro_sum_g_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_G_BIG_MULTIWINDOW_0 1661 u32 ro_sum_b_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_B_BIG_MULTIWINDOW_0 1662 u32 ro_wp_nm_big_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // WP_NM_BIG_MULTIWINDOW_0 1663 u32 ro_sum_r_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_R_SMA_MULTIWINDOW_0 1664 u32 ro_sum_g_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_G_SMA_MULTIWINDOW_0 1665 u32 ro_sum_b_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // SUM_B_SMA_MULTIWINDOW_0 1666 u32 ro_wp_nm_sma_multiwindow[ISP2X_RAWAWB_MULWD_NUM]; // WP_NM_SMA_MULTIWINDOW_0 1667 u32 ro_sum_r_exc[ISP2X_RAWAWB_SUM_NUM]; 1668 u32 ro_sum_g_exc[ISP2X_RAWAWB_SUM_NUM]; 1669 u32 ro_sum_b_exc[ISP2X_RAWAWB_SUM_NUM]; 1670 u32 ro_wp_nm_exc[ISP2X_RAWAWB_SUM_NUM]; 1671 struct isp2x_rawawb_ramdata ramdata[ISP2X_RAWAWB_RAMDATA_NUM]; 1672} __attribute__((packed)); 1673 1674struct isp2x_rawae_meas_data { 1675 u16 channelr_xy; 1676 u16 channelb_xy; 1677 u16 channelg_xy; 1678}; 1679 1680struct isp2x_rawaebig_stat { 1681 u32 sumr[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1682 u32 sumg[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1683 u32 sumb[ISP2X_RAWAEBIG_SUBWIN_NUM]; 1684 struct isp2x_rawae_meas_data data[ISP2X_RAWAEBIG_MEAN_NUM]; 1685} __attribute__((packed)); 1686 1687struct isp2x_rawaelite_stat { 1688 struct isp2x_rawae_meas_data data[ISP2X_RAWAELITE_MEAN_NUM]; 1689} __attribute__((packed)); 1690 1691struct isp2x_yuvae_stat { 1692 u32 ro_yuvae_sumy[ISP2X_YUVAE_SUBWIN_NUM]; 1693 u8 mean[ISP2X_YUVAE_MEAN_NUM]; 1694} __attribute__((packed)); 1695 1696struct isp2x_rawaf_stat { 1697 u32 int_state; 1698 u32 afm_sum[ISP2X_RAWAF_WIN_NUM]; 1699 u32 afm_lum[ISP2X_RAWAF_WIN_NUM]; 1700 u32 ramdata[ISP2X_RAWAF_SUMDATA_NUM]; 1701} __attribute__((packed)); 1702 1703struct isp2x_siaf_meas_val { 1704 u32 sum; 1705 u32 lum; 1706} __attribute__((packed)); 1707 1708struct isp2x_siaf_stat { 1709 struct isp2x_siaf_meas_val win[ISP2X_AFM_MAX_WINDOWS]; 1710} __attribute__((packed)); 1711 1712struct isp2x_rawhistbig_stat { 1713 u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1714} __attribute__((packed)); 1715 1716struct isp2x_rawhistlite_stat { 1717 u32 hist_bin[ISP2X_HIST_BIN_N_MAX]; 1718} __attribute__((packed)); 1719 1720struct isp2x_sihst_win_stat { 1721 u32 hist_bins[ISP2X_SIHIST_BIN_N_MAX]; 1722} __attribute__((packed)); 1723 1724struct isp2x_sihst_stat { 1725 struct isp2x_sihst_win_stat win_stat[ISP2X_SIHIST_WIN_NUM]; 1726} __attribute__((packed)); 1727 1728struct isp2x_stat { 1729 struct isp2x_siawb_stat siawb; 1730 struct isp2x_rawawb_meas_stat rawawb; 1731 struct isp2x_rawaelite_stat rawae0; 1732 struct isp2x_rawaebig_stat rawae1; 1733 struct isp2x_rawaebig_stat rawae2; 1734 struct isp2x_rawaebig_stat rawae3; 1735 struct isp2x_yuvae_stat yuvae; 1736 struct isp2x_rawaf_stat rawaf; 1737 struct isp2x_siaf_stat siaf; 1738 struct isp2x_rawhistlite_stat rawhist0; 1739 struct isp2x_rawhistbig_stat rawhist1; 1740 struct isp2x_rawhistbig_stat rawhist2; 1741 struct isp2x_rawhistbig_stat rawhist3; 1742 struct isp2x_sihst_stat sihst; 1743 1744 struct isp2x_bls_stat bls; 1745 struct isp2x_hdrtmo_stat hdrtmo; 1746 struct isp2x_dhaz_stat dhaz; 1747} __attribute__((packed)); 1748 1749/** 1750 * struct rkisp_isp2x_stat_buffer - Rockchip ISP2 Statistics Meta Data 1751 * 1752 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1753 * @frame_id: frame ID for sync 1754 * @params: statistics data 1755 */ 1756struct rkisp_isp2x_stat_buffer { 1757 unsigned int meas_type; 1758 unsigned int frame_id; 1759 struct isp2x_stat params; 1760} __attribute__((packed)); 1761 1762/** 1763 * struct rkisp_mipi_luma - statistics mipi y statistic 1764 * 1765 * @exp_mean: Mean luminance value of block xx 1766 * 1767 * Image is divided into 5x5 blocks. 1768 */ 1769struct rkisp_mipi_luma { 1770 unsigned int exp_mean[ISP2X_MIPI_LUMA_MEAN_MAX]; 1771} __attribute__((packed)); 1772 1773/** 1774 * struct rkisp_isp2x_luma_buffer - Rockchip ISP1 Statistics Mipi Luma 1775 * 1776 * @meas_type: measurement types (CIFISP_STAT_ definitions) 1777 * @frame_id: frame ID for sync 1778 * @params: statistics data 1779 */ 1780struct rkisp_isp2x_luma_buffer { 1781 unsigned int meas_type; 1782 unsigned int frame_id; 1783 struct rkisp_mipi_luma luma[ISP2X_MIPI_RAW_MAX]; 1784} __attribute__((packed)); 1785 1786/** 1787 * struct rkisp_thunderboot_video_buf 1788 */ 1789struct rkisp_thunderboot_video_buf { 1790 u32 index; 1791 u32 frame_id; 1792 u32 timestamp; 1793 u32 time_reg; 1794 u32 gain_reg; 1795 u32 bufaddr; 1796 u32 bufsize; 1797} __attribute__((packed)); 1798 1799/** 1800 * struct rkisp_thunderboot_resmem_head 1801 */ 1802struct rkisp_thunderboot_resmem_head { 1803 u16 enable; 1804 u16 complete; 1805 u16 frm_total; 1806 u16 hdr_mode; 1807 u16 width; 1808 u16 height; 1809 u32 bus_fmt; 1810 1811 struct rkisp_thunderboot_video_buf l_buf[ISP2X_THUNDERBOOT_VIDEO_BUF_NUM]; 1812 struct rkisp_thunderboot_video_buf m_buf[ISP2X_THUNDERBOOT_VIDEO_BUF_NUM]; 1813 struct rkisp_thunderboot_video_buf s_buf[ISP2X_THUNDERBOOT_VIDEO_BUF_NUM]; 1814} __attribute__((packed)); 1815 1816/** 1817 * struct rkisp_thunderboot_resmem - shared buffer for thunderboot with risc-v side 1818 */ 1819struct rkisp_thunderboot_resmem { 1820 u32 resmem_padr; 1821 u32 resmem_size; 1822} __attribute__((packed)); 1823 1824/** 1825 * struct rkisp_thunderboot_shmem 1826 */ 1827struct rkisp_thunderboot_shmem { 1828 u32 shm_start; 1829 u32 shm_size; 1830 s32 shm_fd; 1831} __attribute__((packed)); 1832 1833#endif /* _UAPI_RKISP2_CONFIG_H */ 1834