13d0407baSopenharmony_ci/* SPDX-License-Identifier: GPL-2.0 */ 23d0407baSopenharmony_ci#ifndef _LINUX_MMU_CONTEXT_H 33d0407baSopenharmony_ci#define _LINUX_MMU_CONTEXT_H 43d0407baSopenharmony_ci 53d0407baSopenharmony_ci#include <asm/mmu_context.h> 63d0407baSopenharmony_ci#include <asm/mmu.h> 73d0407baSopenharmony_ci 83d0407baSopenharmony_ci/* Architectures that care about IRQ state in switch_mm can override this. */ 93d0407baSopenharmony_ci#ifndef switch_mm_irqs_off 103d0407baSopenharmony_ci#define switch_mm_irqs_off switch_mm 113d0407baSopenharmony_ci#endif 123d0407baSopenharmony_ci 133d0407baSopenharmony_ci#ifndef leave_mm 143d0407baSopenharmony_cistatic inline void leave_mm(int cpu) 153d0407baSopenharmony_ci{ 163d0407baSopenharmony_ci} 173d0407baSopenharmony_ci#endif 183d0407baSopenharmony_ci 193d0407baSopenharmony_ci/* 203d0407baSopenharmony_ci * CPUs that are capable of running task @p. By default, we assume a sane, 213d0407baSopenharmony_ci * homogeneous system. Must contain at least one active CPU. 223d0407baSopenharmony_ci */ 233d0407baSopenharmony_ci#ifndef task_cpu_possible_mask 243d0407baSopenharmony_ci#define task_cpu_possible_mask(p) cpu_possible_mask 253d0407baSopenharmony_ci#endif 263d0407baSopenharmony_ci 273d0407baSopenharmony_ci#endif 28