1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2018 Rockchip Electronics Co., Ltd.
4 */
5
6#ifndef ROCKCHIP_PCIE_DMA_H
7#define ROCKCHIP_PCIE_DMA_H
8
9#include <linux/debugfs.h>
10
11#define PCIE_DMA_TABLE_NUM 24
12
13#define PCIE_DMA_TRX_TYPE_NUM 3
14
15#define PCIE_DMA_CHN0 0x0
16
17#define PCIE_DMA_DATA_SND_TABLE_OFFSET 0x0
18#define PCIE_DMA_DATA_RCV_ACK_TABLE_OFFSET 0x8
19#define PCIE_DMA_DATA_FREE_ACK_TABLE_OFFSET 0x10
20
21enum dma_dir {
22    DMA_FROM_BUS,
23    DMA_TO_BUS,
24};
25
26/**
27 * The Channel Control Register for read and write.
28 */
29union chan_ctrl_lo {
30    struct {
31        u32 cb : 1;    // 0
32        u32 tcb : 1;   // 1
33        u32 llp : 1;   // 2
34        u32 lie : 1;   // 3
35        u32 rie : 1;   // 4
36        u32 cs : 2;    // 5:6
37        u32 rsvd1 : 1; // 7
38        u32 ccs : 1;   // 8
39        u32 llen : 1;  // 9
40        u32 b_64s : 1; // 10
41        u32 b_64d : 1; // 11
42        u32 pf : 5;    // 12:16
43        u32 rsvd2 : 7; // 17:23
44        u32 sn : 1;    // 24
45        u32 ro : 1;    // 25
46        u32 td : 1;    // 26
47        u32 tc : 3;    // 27:29
48        u32 at : 2;    // 30:31
49    };
50    u32 asdword;
51};
52
53/**
54 * The Channel Control Register high part for read and write.
55 */
56union chan_ctrl_hi {
57    struct {
58        u32 vfenb : 1;  // 0
59        u32 vfunc : 8;  // 1-8
60        u32 rsvd0 : 23; // 9-31
61    };
62    u32 asdword;
63};
64
65/**
66 * The Channel Weight Register.
67 */
68union weight {
69    struct {
70        u32 weight0 : 5; // 0:4
71        u32 weight1 : 5; // 5:9
72        u32 weight2 : 5; // 10:14
73        u32 weight3 : 5; // 15:19
74        u32 rsvd : 12;   // 20:31
75    };
76    u32 asdword;
77};
78
79/**
80 * The Doorbell Register for read and write.
81 */
82union db {
83    struct {
84        u32 chnl : 3;       // 0
85        u32 reserved0 : 28; // 3:30
86        u32 stop : 1;       // 31
87    };
88    u32 asdword;
89};
90
91/**
92 * The Context Registers for read and write.
93 */
94struct ctx_regs {
95    union chan_ctrl_lo ctrllo;
96    union chan_ctrl_hi ctrlhi;
97    u32 xfersize;
98    u32 sarptrlo;
99    u32 sarptrhi;
100    u32 darptrlo;
101    u32 darptrhi;
102};
103
104/**
105 * The Enable Register for read and write.
106 */
107union enb {
108    struct {
109        u32 enb : 1;        // 0
110        u32 reserved0 : 31; // 1:31
111    };
112    u32 asdword;
113};
114
115/**
116 * The Interrupt Status Register for read and write.
117 */
118union int_status {
119    struct {
120        u32 donesta : 8;
121        u32 rsvd0 : 8;
122        u32 abortsta : 8;
123        u32 rsvd1 : 8;
124    };
125    u32 asdword;
126};
127
128/**
129 * The Interrupt Clear Register for read and write.
130 */
131union int_clear {
132    struct {
133        u32 doneclr : 8;
134        u32 rsvd0 : 8;
135        u32 abortclr : 8;
136        u32 rsvd1 : 8;
137    };
138    u32 asdword;
139};
140
141struct dma_table {
142    u32 *descs;
143    int chn;
144    phys_addr_t phys_descs;
145    u32 dir;
146    u32 type;
147    struct list_head tbl_node;
148    union enb wr_enb;
149    struct ctx_regs ctx_reg;
150    union weight wr_weilo;
151    union weight wr_weihi;
152    union db start;
153    phys_addr_t local;
154    phys_addr_t bus;
155    size_t buf_size;
156};
157
158struct dma_trx_obj {
159    struct device *dev;
160    int loop_count;
161    int loop_count_threshold;
162    void *mem_base;
163    phys_addr_t mem_start;
164    size_t mem_size;
165    int dma_free;
166    unsigned long local_write_available;
167    unsigned long local_read_available;
168    unsigned long remote_write_available;
169    spinlock_t tbl_list_lock; /* lock dma table */
170    struct list_head tbl_list;
171    struct work_struct dma_trx_work;
172    wait_queue_head_t event_queue;
173    struct workqueue_struct *dma_trx_wq;
174    struct dma_table *table[PCIE_DMA_TABLE_NUM];
175    struct dma_table *cur;
176    struct task_struct *scan_thread;
177    struct hrtimer scan_timer;
178    int busno;
179    void *priv;
180    struct completion done;
181    int ref_count;
182    struct mutex count_mutex;
183    unsigned long irq_num;
184    struct dentry *pcie_root;
185    struct pcie_misc_dev *pcie_dev;
186    void (*start_dma_func)(struct dma_trx_obj *obj);
187    void (*config_dma_func)(struct dma_table *table);
188};
189
190#ifdef CONFIG_ROCKCHIP_PCIE_DMA_OBJ
191struct dma_trx_obj *rk_pcie_dma_obj_probe(struct device *dev);
192void rk_pcie_dma_obj_remove(struct dma_trx_obj *obj);
193#else
194static inline struct dma_trx_obj *rk_pcie_dma_obj_probe(struct device *dev)
195{
196    return NULL;
197}
198
199static inline void rk_pcie_dma_obj_remove(struct dma_trx_obj *obj)
200{
201}
202#endif
203
204#endif /* ROCKCHIP_PCIE_DMA_H */
205