1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Rockchip AXI PCIe host controller driver
4 *
5 * Copyright (c) 2016 Rockchip, Inc.
6 *
7 * Author: Shawn Lin <shawn.lin@rock-chips.com>
8 *         Wenrui Li <wenrui.li@rock-chips.com>
9 *
10 * Bits taken from Synopsys DesignWare Host controller driver and
11 * ARM PCI Host generic driver.
12 */
13
14#include <linux/clk.h>
15#include <linux/delay.h>
16#include <linux/gpio/consumer.h>
17#include <linux/module.h>
18#include <linux/of_pci.h>
19#include <linux/phy/phy.h>
20#include <linux/platform_device.h>
21#include <linux/reset.h>
22
23#include "../pci.h"
24#include "pcie-rockchip.h"
25
26#define RK_PCIE_LANES_THREE 3
27#define RK_PCIE_LANES_FOUR 4
28#define RK_PCIE_LINK_GEN_MAX 2
29#define RK_PCIE_INIT_UDELAY 10
30#define RK_PCIE_CFG_BIT_MASK 23
31
32int rockchip_pcie_get_phys(struct rockchip_pcie *rockchip)
33{
34    struct device *dev = rockchip->dev;
35    struct phy *phy;
36    char *name;
37    u32 i;
38
39    phy = devm_phy_get(dev, "pcie-phy");
40    if (!IS_ERR(phy)) {
41        rockchip->legacy_phy = true;
42        rockchip->phys[0] = phy;
43        dev_warn(dev, "legacy phy model is deprecated!\n");
44        return 0;
45    }
46
47    if (PTR_ERR(phy) == -EPROBE_DEFER) {
48        return PTR_ERR(phy);
49    }
50
51    dev_dbg(dev, "missing legacy phy; search for per-lane PHY\n");
52
53    for (i = 0; i < MAX_LANE_NUM; i++) {
54        name = kasprintf(GFP_KERNEL, "pcie-phy-%u", i);
55        if (!name) {
56            return -ENOMEM;
57        }
58
59        phy = devm_of_phy_get(dev, dev->of_node, name);
60        kfree(name);
61
62        if (IS_ERR(phy)) {
63            if (PTR_ERR(phy) != -EPROBE_DEFER) {
64                dev_err(dev, "missing phy for lane %d: %ld\n", i, PTR_ERR(phy));
65            }
66            return PTR_ERR(phy);
67        }
68
69        rockchip->phys[i] = phy;
70    }
71
72    return 0;
73}
74EXPORT_SYMBOL_GPL(rockchip_pcie_get_phys);
75
76int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
77{
78    struct device *dev = rockchip->dev;
79    struct platform_device *pdev = to_platform_device(dev);
80    struct device_node *node = dev->of_node;
81    struct resource *regs;
82    int err;
83
84    if (rockchip->is_rc) {
85        regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "axi-base");
86        rockchip->reg_base = devm_pci_remap_cfg_resource(dev, regs);
87        if (IS_ERR(rockchip->reg_base)) {
88            return PTR_ERR(rockchip->reg_base);
89        }
90    } else {
91        rockchip->mem_res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem-base");
92        if (!rockchip->mem_res) {
93            return -EINVAL;
94        }
95    }
96
97    rockchip->apb_base = devm_platform_ioremap_resource_byname(pdev, "apb-base");
98    if (IS_ERR(rockchip->apb_base)) {
99        return PTR_ERR(rockchip->apb_base);
100    }
101
102    err = rockchip_pcie_get_phys(rockchip);
103    if (err) {
104        return err;
105    }
106
107    rockchip->lanes = 1;
108    err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
109    if (!err &&
110        (rockchip->lanes == 0 || rockchip->lanes == RK_PCIE_LANES_THREE || rockchip->lanes > RK_PCIE_LANES_FOUR)) {
111        dev_warn(dev, "invalid num-lanes, default to use one lane\n");
112        rockchip->lanes = 1;
113    }
114
115    rockchip->link_gen = of_pci_get_max_link_speed(node);
116    if (rockchip->link_gen < 0 || rockchip->link_gen > RK_PCIE_LINK_GEN_MAX) {
117        rockchip->link_gen = RK_PCIE_LINK_GEN_MAX;
118    }
119
120    rockchip->core_rst = devm_reset_control_get_exclusive(dev, "core");
121    if (IS_ERR(rockchip->core_rst)) {
122        if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER) {
123            dev_err(dev, "missing core reset property in node\n");
124        }
125        return PTR_ERR(rockchip->core_rst);
126    }
127
128    rockchip->mgmt_rst = devm_reset_control_get_exclusive(dev, "mgmt");
129    if (IS_ERR(rockchip->mgmt_rst)) {
130        if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER) {
131            dev_err(dev, "missing mgmt reset property in node\n");
132        }
133        return PTR_ERR(rockchip->mgmt_rst);
134    }
135
136    rockchip->mgmt_sticky_rst = devm_reset_control_get_exclusive(dev, "mgmt-sticky");
137    if (IS_ERR(rockchip->mgmt_sticky_rst)) {
138        if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER) {
139            dev_err(dev, "missing mgmt-sticky reset property in node\n");
140        }
141        return PTR_ERR(rockchip->mgmt_sticky_rst);
142    }
143
144    rockchip->pipe_rst = devm_reset_control_get_exclusive(dev, "pipe");
145    if (IS_ERR(rockchip->pipe_rst)) {
146        if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER) {
147            dev_err(dev, "missing pipe reset property in node\n");
148        }
149        return PTR_ERR(rockchip->pipe_rst);
150    }
151
152    rockchip->pm_rst = devm_reset_control_get_exclusive(dev, "pm");
153    if (IS_ERR(rockchip->pm_rst)) {
154        if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER) {
155            dev_err(dev, "missing pm reset property in node\n");
156        }
157        return PTR_ERR(rockchip->pm_rst);
158    }
159
160    rockchip->pclk_rst = devm_reset_control_get_exclusive(dev, "pclk");
161    if (IS_ERR(rockchip->pclk_rst)) {
162        if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER) {
163            dev_err(dev, "missing pclk reset property in node\n");
164        }
165        return PTR_ERR(rockchip->pclk_rst);
166    }
167
168    rockchip->aclk_rst = devm_reset_control_get_exclusive(dev, "aclk");
169    if (IS_ERR(rockchip->aclk_rst)) {
170        if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER) {
171            dev_err(dev, "missing aclk reset property in node\n");
172        }
173        return PTR_ERR(rockchip->aclk_rst);
174    }
175
176    if (rockchip->is_rc) {
177        rockchip->ep_gpio = devm_gpiod_get_optional(dev, "ep", GPIOD_OUT_HIGH);
178        if (IS_ERR(rockchip->ep_gpio)) {
179            return dev_err_probe(dev, PTR_ERR(rockchip->ep_gpio), "failed to get ep GPIO\n");
180        }
181    }
182
183    rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
184    if (IS_ERR(rockchip->aclk_pcie)) {
185        dev_err(dev, "aclk clock not found\n");
186        return PTR_ERR(rockchip->aclk_pcie);
187    }
188
189    rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
190    if (IS_ERR(rockchip->aclk_perf_pcie)) {
191        dev_err(dev, "aclk_perf clock not found\n");
192        return PTR_ERR(rockchip->aclk_perf_pcie);
193    }
194
195    rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
196    if (IS_ERR(rockchip->hclk_pcie)) {
197        dev_err(dev, "hclk clock not found\n");
198        return PTR_ERR(rockchip->hclk_pcie);
199    }
200
201    rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
202    if (IS_ERR(rockchip->clk_pcie_pm)) {
203        dev_err(dev, "pm clock not found\n");
204        return PTR_ERR(rockchip->clk_pcie_pm);
205    }
206
207    return 0;
208}
209EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
210
211int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
212{
213    struct device *dev = rockchip->dev;
214    int err, i;
215    u32 regs;
216
217    err = reset_control_assert(rockchip->aclk_rst);
218    if (err) {
219        dev_err(dev, "assert aclk_rst err %d\n", err);
220        return err;
221    }
222
223    err = reset_control_assert(rockchip->pclk_rst);
224    if (err) {
225        dev_err(dev, "assert pclk_rst err %d\n", err);
226        return err;
227    }
228
229    err = reset_control_assert(rockchip->pm_rst);
230    if (err) {
231        dev_err(dev, "assert pm_rst err %d\n", err);
232        return err;
233    }
234
235    for (i = 0; i < MAX_LANE_NUM; i++) {
236        err = phy_init(rockchip->phys[i]);
237        if (err) {
238            dev_err(dev, "init phy%d err %d\n", i, err);
239            goto err_exit_phy;
240        }
241    }
242
243    err = reset_control_assert(rockchip->core_rst);
244    if (err) {
245        dev_err(dev, "assert core_rst err %d\n", err);
246        goto err_exit_phy;
247    }
248
249    err = reset_control_assert(rockchip->mgmt_rst);
250    if (err) {
251        dev_err(dev, "assert mgmt_rst err %d\n", err);
252        goto err_exit_phy;
253    }
254
255    err = reset_control_assert(rockchip->mgmt_sticky_rst);
256    if (err) {
257        dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
258        goto err_exit_phy;
259    }
260
261    err = reset_control_assert(rockchip->pipe_rst);
262    if (err) {
263        dev_err(dev, "assert pipe_rst err %d\n", err);
264        goto err_exit_phy;
265    }
266
267    udelay(RK_PCIE_INIT_UDELAY);
268
269    err = reset_control_deassert(rockchip->pm_rst);
270    if (err) {
271        dev_err(dev, "deassert pm_rst err %d\n", err);
272        goto err_exit_phy;
273    }
274
275    err = reset_control_deassert(rockchip->aclk_rst);
276    if (err) {
277        dev_err(dev, "deassert aclk_rst err %d\n", err);
278        goto err_exit_phy;
279    }
280
281    err = reset_control_deassert(rockchip->pclk_rst);
282    if (err) {
283        dev_err(dev, "deassert pclk_rst err %d\n", err);
284        goto err_exit_phy;
285    }
286
287    if (rockchip->link_gen == RK_PCIE_LINK_GEN_MAX) {
288        rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2, PCIE_CLIENT_CONFIG);
289    } else {
290        rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1, PCIE_CLIENT_CONFIG);
291    }
292
293    regs = PCIE_CLIENT_LINK_TRAIN_ENABLE | PCIE_CLIENT_ARI_ENABLE | PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes);
294
295    if (rockchip->is_rc) {
296        regs |= PCIE_CLIENT_CONF_ENABLE | PCIE_CLIENT_MODE_RC;
297    } else {
298        regs |= PCIE_CLIENT_CONF_DISABLE | PCIE_CLIENT_MODE_EP;
299    }
300
301    rockchip_pcie_write(rockchip, regs, PCIE_CLIENT_CONFIG);
302
303    for (i = 0; i < MAX_LANE_NUM; i++) {
304        err = phy_power_on(rockchip->phys[i]);
305        if (err) {
306            dev_err(dev, "power on phy%d err %d\n", i, err);
307            goto err_power_off_phy;
308        }
309    }
310
311    /*
312     * Please don't reorder the deassert sequence of the following
313     * four reset pins.
314     */
315    err = reset_control_deassert(rockchip->mgmt_sticky_rst);
316    if (err) {
317        dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
318        goto err_power_off_phy;
319    }
320
321    err = reset_control_deassert(rockchip->core_rst);
322    if (err) {
323        dev_err(dev, "deassert core_rst err %d\n", err);
324        goto err_power_off_phy;
325    }
326
327    err = reset_control_deassert(rockchip->mgmt_rst);
328    if (err) {
329        dev_err(dev, "deassert mgmt_rst err %d\n", err);
330        goto err_power_off_phy;
331    }
332
333    err = reset_control_deassert(rockchip->pipe_rst);
334    if (err) {
335        dev_err(dev, "deassert pipe_rst err %d\n", err);
336        goto err_power_off_phy;
337    }
338
339    return 0;
340err_power_off_phy:
341    while (i--) {
342        phy_power_off(rockchip->phys[i]);
343    }
344    i = MAX_LANE_NUM;
345err_exit_phy:
346    while (i--) {
347        phy_exit(rockchip->phys[i]);
348    }
349    return err;
350}
351EXPORT_SYMBOL_GPL(rockchip_pcie_init_port);
352
353void rockchip_pcie_deinit_phys(struct rockchip_pcie *rockchip)
354{
355    int i;
356
357    for (i = 0; i < MAX_LANE_NUM; i++) {
358        /* inactive lanes are already powered off */
359        if (rockchip->lanes_map & BIT(i)) {
360            phy_power_off(rockchip->phys[i]);
361        }
362        phy_exit(rockchip->phys[i]);
363    }
364}
365EXPORT_SYMBOL_GPL(rockchip_pcie_deinit_phys);
366
367int rockchip_pcie_enable_clocks(struct rockchip_pcie *rockchip)
368{
369    struct device *dev = rockchip->dev;
370    int err;
371
372    err = clk_prepare_enable(rockchip->aclk_pcie);
373    if (err) {
374        dev_err(dev, "unable to enable aclk_pcie clock\n");
375        return err;
376    }
377
378    err = clk_prepare_enable(rockchip->aclk_perf_pcie);
379    if (err) {
380        dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
381        goto err_aclk_perf_pcie;
382    }
383
384    err = clk_prepare_enable(rockchip->hclk_pcie);
385    if (err) {
386        dev_err(dev, "unable to enable hclk_pcie clock\n");
387        goto err_hclk_pcie;
388    }
389
390    err = clk_prepare_enable(rockchip->clk_pcie_pm);
391    if (err) {
392        dev_err(dev, "unable to enable clk_pcie_pm clock\n");
393        goto err_clk_pcie_pm;
394    }
395
396    return 0;
397
398err_clk_pcie_pm:
399    clk_disable_unprepare(rockchip->hclk_pcie);
400err_hclk_pcie:
401    clk_disable_unprepare(rockchip->aclk_perf_pcie);
402err_aclk_perf_pcie:
403    clk_disable_unprepare(rockchip->aclk_pcie);
404    return err;
405}
406EXPORT_SYMBOL_GPL(rockchip_pcie_enable_clocks);
407
408void rockchip_pcie_disable_clocks(void *data)
409{
410    struct rockchip_pcie *rockchip = data;
411
412    clk_disable_unprepare(rockchip->clk_pcie_pm);
413    clk_disable_unprepare(rockchip->hclk_pcie);
414    clk_disable_unprepare(rockchip->aclk_perf_pcie);
415    clk_disable_unprepare(rockchip->aclk_pcie);
416}
417EXPORT_SYMBOL_GPL(rockchip_pcie_disable_clocks);
418
419void rockchip_pcie_cfg_configuration_accesses(struct rockchip_pcie *rockchip, u32 type)
420{
421    u32 ob_desc_0;
422
423    /* Configuration Accesses for region 0 */
424    rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
425
426    rockchip_pcie_write(rockchip, (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS), PCIE_CORE_OB_REGION_ADDR0);
427    rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H, PCIE_CORE_OB_REGION_ADDR1);
428    ob_desc_0 = rockchip_pcie_read(rockchip, PCIE_CORE_OB_REGION_DESC0);
429    ob_desc_0 &= ~(RC_REGION_0_TYPE_MASK);
430    ob_desc_0 |= (type | (0x1 << RK_PCIE_CFG_BIT_MASK));
431    rockchip_pcie_write(rockchip, ob_desc_0, PCIE_CORE_OB_REGION_DESC0);
432    rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
433}
434EXPORT_SYMBOL_GPL(rockchip_pcie_cfg_configuration_accesses);
435
436MODULE_AUTHOR("Rockchip Inc");
437MODULE_DESCRIPTION("Rockchip AXI PCIe driver");
438MODULE_LICENSE("GPL v2");
439