1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Record and handle CPU attributes. 4 * 5 * Copyright (C) 2014 ARM Ltd. 6 */ 7#include <asm/arch_timer.h> 8#include <asm/cache.h> 9#include <asm/cpu.h> 10#include <asm/cputype.h> 11#include <asm/cpufeature.h> 12#include <asm/fpsimd.h> 13 14#include <linux/bitops.h> 15#include <linux/bug.h> 16#include <linux/compat.h> 17#include <linux/elf.h> 18#include <linux/init.h> 19#include <linux/kernel.h> 20#include <linux/personality.h> 21#include <linux/preempt.h> 22#include <linux/printk.h> 23#include <linux/seq_file.h> 24#include <linux/sched.h> 25#include <linux/smp.h> 26#include <linux/delay.h> 27 28unsigned int system_serial_low; 29EXPORT_SYMBOL(system_serial_low); 30 31unsigned int system_serial_high; 32EXPORT_SYMBOL(system_serial_high); 33 34/* 35 * In case the boot CPU is hotpluggable, we record its initial state and 36 * current state separately. Certain system registers may contain different 37 * values depending on configuration at or after reset. 38 */ 39DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); 40static struct cpuinfo_arm64 boot_cpu_data; 41 42static const char *icache_policy_str[] = { 43 [ICACHE_POLICY_VPIPT] = "VPIPT", 44 [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", 45 [ICACHE_POLICY_VIPT] = "VIPT", 46 [ICACHE_POLICY_PIPT] = "PIPT", 47}; 48 49unsigned long __icache_flags; 50 51static const char *const hwcap_str[] = { 52 [KERNEL_HWCAP_FP] = "fp", 53 [KERNEL_HWCAP_ASIMD] = "asimd", 54 [KERNEL_HWCAP_EVTSTRM] = "evtstrm", 55 [KERNEL_HWCAP_AES] = "aes", 56 [KERNEL_HWCAP_PMULL] = "pmull", 57 [KERNEL_HWCAP_SHA1] = "sha1", 58 [KERNEL_HWCAP_SHA2] = "sha2", 59 [KERNEL_HWCAP_CRC32] = "crc32", 60 [KERNEL_HWCAP_ATOMICS] = "atomics", 61 [KERNEL_HWCAP_FPHP] = "fphp", 62 [KERNEL_HWCAP_ASIMDHP] = "asimdhp", 63 [KERNEL_HWCAP_CPUID] = "cpuid", 64 [KERNEL_HWCAP_ASIMDRDM] = "asimdrdm", 65 [KERNEL_HWCAP_JSCVT] = "jscvt", 66 [KERNEL_HWCAP_FCMA] = "fcma", 67 [KERNEL_HWCAP_LRCPC] = "lrcpc", 68 [KERNEL_HWCAP_DCPOP] = "dcpop", 69 [KERNEL_HWCAP_SHA3] = "sha3", 70 [KERNEL_HWCAP_SM3] = "sm3", 71 [KERNEL_HWCAP_SM4] = "sm4", 72 [KERNEL_HWCAP_ASIMDDP] = "asimddp", 73 [KERNEL_HWCAP_SHA512] = "sha512", 74 [KERNEL_HWCAP_SVE] = "sve", 75 [KERNEL_HWCAP_ASIMDFHM] = "asimdfhm", 76 [KERNEL_HWCAP_DIT] = "dit", 77 [KERNEL_HWCAP_USCAT] = "uscat", 78 [KERNEL_HWCAP_ILRCPC] = "ilrcpc", 79 [KERNEL_HWCAP_FLAGM] = "flagm", 80 [KERNEL_HWCAP_SSBS] = "ssbs", 81 [KERNEL_HWCAP_SB] = "sb", 82 [KERNEL_HWCAP_PACA] = "paca", 83 [KERNEL_HWCAP_PACG] = "pacg", 84 [KERNEL_HWCAP_DCPODP] = "dcpodp", 85 [KERNEL_HWCAP_SVE2] = "sve2", 86 [KERNEL_HWCAP_SVEAES] = "sveaes", 87 [KERNEL_HWCAP_SVEPMULL] = "svepmull", 88 [KERNEL_HWCAP_SVEBITPERM] = "svebitperm", 89 [KERNEL_HWCAP_SVESHA3] = "svesha3", 90 [KERNEL_HWCAP_SVESM4] = "svesm4", 91 [KERNEL_HWCAP_FLAGM2] = "flagm2", 92 [KERNEL_HWCAP_FRINT] = "frint", 93 [KERNEL_HWCAP_SVEI8MM] = "svei8mm", 94 [KERNEL_HWCAP_SVEF32MM] = "svef32mm", 95 [KERNEL_HWCAP_SVEF64MM] = "svef64mm", 96 [KERNEL_HWCAP_SVEBF16] = "svebf16", 97 [KERNEL_HWCAP_I8MM] = "i8mm", 98 [KERNEL_HWCAP_BF16] = "bf16", 99 [KERNEL_HWCAP_DGH] = "dgh", 100 [KERNEL_HWCAP_RNG] = "rng", 101 [KERNEL_HWCAP_BTI] = "bti", 102 [KERNEL_HWCAP_MTE] = "mte", 103 [KERNEL_HWCAP_ECV] = "ecv", 104 [KERNEL_HWCAP_AFP] = "afp", 105 [KERNEL_HWCAP_RPRES] = "rpres", 106}; 107 108#ifdef CONFIG_COMPAT 109#define COMPAT_KERNEL_HWCAP(x) const_ilog2(COMPAT_HWCAP_##x) 110static const char *const compat_hwcap_str[] = { 111 [COMPAT_KERNEL_HWCAP(SWP)] = "swp", 112 [COMPAT_KERNEL_HWCAP(HALF)] = "half", 113 [COMPAT_KERNEL_HWCAP(THUMB)] = "thumb", 114 [COMPAT_KERNEL_HWCAP(26BIT)] = NULL, /* Not possible on arm64 */ 115 [COMPAT_KERNEL_HWCAP(FAST_MULT)] = "fastmult", 116 [COMPAT_KERNEL_HWCAP(FPA)] = NULL, /* Not possible on arm64 */ 117 [COMPAT_KERNEL_HWCAP(VFP)] = "vfp", 118 [COMPAT_KERNEL_HWCAP(EDSP)] = "edsp", 119 [COMPAT_KERNEL_HWCAP(JAVA)] = NULL, /* Not possible on arm64 */ 120 [COMPAT_KERNEL_HWCAP(IWMMXT)] = NULL, /* Not possible on arm64 */ 121 [COMPAT_KERNEL_HWCAP(CRUNCH)] = NULL, /* Not possible on arm64 */ 122 [COMPAT_KERNEL_HWCAP(THUMBEE)] = NULL, /* Not possible on arm64 */ 123 [COMPAT_KERNEL_HWCAP(NEON)] = "neon", 124 [COMPAT_KERNEL_HWCAP(VFPv3)] = "vfpv3", 125 [COMPAT_KERNEL_HWCAP(VFPV3D16)] = NULL, /* Not possible on arm64 */ 126 [COMPAT_KERNEL_HWCAP(TLS)] = "tls", 127 [COMPAT_KERNEL_HWCAP(VFPv4)] = "vfpv4", 128 [COMPAT_KERNEL_HWCAP(IDIVA)] = "idiva", 129 [COMPAT_KERNEL_HWCAP(IDIVT)] = "idivt", 130 [COMPAT_KERNEL_HWCAP(VFPD32)] = NULL, /* Not possible on arm64 */ 131 [COMPAT_KERNEL_HWCAP(LPAE)] = "lpae", 132 [COMPAT_KERNEL_HWCAP(EVTSTRM)] = "evtstrm", 133}; 134 135#define COMPAT_KERNEL_HWCAP2(x) const_ilog2(COMPAT_HWCAP2_##x) 136static const char *const compat_hwcap2_str[] = { 137 [COMPAT_KERNEL_HWCAP2(AES)] = "aes", [COMPAT_KERNEL_HWCAP2(PMULL)] = "pmull", 138 [COMPAT_KERNEL_HWCAP2(SHA1)] = "sha1", [COMPAT_KERNEL_HWCAP2(SHA2)] = "sha2", 139 [COMPAT_KERNEL_HWCAP2(CRC32)] = "crc32", 140}; 141#endif /* CONFIG_COMPAT */ 142 143static int c_show(struct seq_file *m, void *v) 144{ 145 int i, j; 146 bool compat = personality(current->personality) == PER_LINUX32; 147 148 for_each_online_cpu(i) 149 { 150 struct cpuinfo_arm64 *cpuinfo = &per_cpu(cpu_data, i); 151 u32 midr = cpuinfo->reg_midr; 152 153 /* 154 * glibc reads /proc/cpuinfo to determine the number of 155 * online processors, looking for lines beginning with 156 * "processor". Give glibc what it expects. 157 */ 158 seq_printf(m, "processor\t: %d\n", i); 159 if (compat) { 160 seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n", MIDR_REVISION(midr), COMPAT_ELF_PLATFORM); 161 } 162 163 seq_printf(m, "BogoMIPS\t: %lu.%02lu\n", loops_per_jiffy / (500000UL / HZ), 164 loops_per_jiffy / (5000UL / HZ) % 0x64); 165 166 /* 167 * Dump out the common processor features in a single line. 168 * Userspace should read the hwcaps with getauxval(AT_HWCAP) 169 * rather than attempting to parse this, but there's a body of 170 * software which does already (at least for 32-bit). 171 */ 172 seq_puts(m, "Features\t:"); 173 if (compat) { 174#ifdef CONFIG_COMPAT 175 for (j = 0; j < ARRAY_SIZE(compat_hwcap_str); j++) { 176 if (compat_elf_hwcap & (1 << j)) { 177 /* 178 * Warn once if any feature should not 179 * have been present on arm64 platform. 180 */ 181 if (WARN_ON_ONCE(!compat_hwcap_str[j])) { 182 continue; 183 } 184 185 seq_printf(m, " %s", compat_hwcap_str[j]); 186 } 187 } 188 189 for (j = 0; j < ARRAY_SIZE(compat_hwcap2_str); j++) { 190 if (compat_elf_hwcap2 & (1 << j)) { 191 seq_printf(m, " %s", compat_hwcap2_str[j]); 192 } 193 } 194#endif /* CONFIG_COMPAT */ 195 } else { 196 for (j = 0; j < ARRAY_SIZE(hwcap_str); j++) { 197 if (cpu_have_feature(j)) { 198 seq_printf(m, " %s", hwcap_str[j]); 199 } 200 } 201 } 202 seq_puts(m, "\n"); 203 204 seq_printf(m, "CPU implementer\t: 0x%02x\n", MIDR_IMPLEMENTOR(midr)); 205 seq_printf(m, "CPU architecture: 8\n"); 206 seq_printf(m, "CPU variant\t: 0x%x\n", MIDR_VARIANT(midr)); 207 seq_printf(m, "CPU part\t: 0x%03x\n", MIDR_PARTNUM(midr)); 208 seq_printf(m, "CPU revision\t: %d\n\n", MIDR_REVISION(midr)); 209 } 210 211 return 0; 212} 213 214static void *c_start(struct seq_file *m, loff_t *pos) 215{ 216 return *pos < 1 ? (void *)1 : NULL; 217} 218 219static void *c_next(struct seq_file *m, void *v, loff_t *pos) 220{ 221 ++*pos; 222 return NULL; 223} 224 225static void c_stop(struct seq_file *m, void *v) 226{ 227} 228 229const struct seq_operations cpuinfo_op = {.start = c_start, .next = c_next, .stop = c_stop, .show = c_show}; 230 231static struct kobj_type cpuregs_kobj_type = { 232 .sysfs_ops = &kobj_sysfs_ops, 233}; 234 235/* 236 * The ARM ARM uses the phrase "32-bit register" to describe a register 237 * whose upper 32 bits are RES0 (per C5.1.1, ARM DDI 0487A.i), however 238 * no statement is made as to whether the upper 32 bits will or will not 239 * be made use of in future, and between ARM DDI 0487A.c and ARM DDI 240 * 0487A.d CLIDR_EL1 was expanded from 32-bit to 64-bit. 241 * 242 * Thus, while both MIDR_EL1 and REVIDR_EL1 are described as 32-bit 243 * registers, we expose them both as 64 bit values to cater for possible 244 * future expansion without an ABI break. 245 */ 246#define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) 247#define CPUREGS_ATTR_RO(_name, _field) \ 248 static ssize_t _name##_show(struct kobject *kobj, struct kobj_attribute *attr, char *buf) \ 249 { \ 250 struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ 251 \ 252 if (info->reg_midr) \ 253 return sprintf(buf, "0x%016x\n", info->reg_##_field); \ 254 else \ 255 return 0; \ 256 } \ 257 static struct kobj_attribute cpuregs_attr_##_name = __ATTR_RO(_name) 258 259CPUREGS_ATTR_RO(midr_el1, midr); 260CPUREGS_ATTR_RO(revidr_el1, revidr); 261 262static struct attribute *cpuregs_id_attrs[] = {&cpuregs_attr_midr_el1.attr, &cpuregs_attr_revidr_el1.attr, NULL}; 263 264static const struct attribute_group cpuregs_attr_group = {.attrs = cpuregs_id_attrs, .name = "identification"}; 265 266static int cpuid_cpu_online(unsigned int cpu) 267{ 268 int rc; 269 struct device *dev; 270 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 271 272 dev = get_cpu_device(cpu); 273 if (!dev) { 274 rc = -ENODEV; 275 goto out; 276 } 277 rc = kobject_add(&info->kobj, &dev->kobj, "regs"); 278 if (rc) { 279 goto out; 280 } 281 rc = sysfs_create_group(&info->kobj, &cpuregs_attr_group); 282 if (rc) { 283 kobject_del(&info->kobj); 284 } 285out: 286 return rc; 287} 288 289static int cpuid_cpu_offline(unsigned int cpu) 290{ 291 struct device *dev; 292 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 293 294 dev = get_cpu_device(cpu); 295 if (!dev) { 296 return -ENODEV; 297 } 298 if (info->kobj.parent) { 299 sysfs_remove_group(&info->kobj, &cpuregs_attr_group); 300 kobject_del(&info->kobj); 301 } 302 303 return 0; 304} 305 306static int __init cpuinfo_regs_init(void) 307{ 308 int cpu, ret; 309 310 for_each_possible_cpu(cpu) 311 { 312 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); 313 314 kobject_init(&info->kobj, &cpuregs_kobj_type); 315 } 316 317 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "arm64/cpuinfo:online", cpuid_cpu_online, cpuid_cpu_offline); 318 if (ret < 0) { 319 pr_err("cpuinfo: failed to register hotplug callbacks.\n"); 320 return ret; 321 } 322 return 0; 323} 324device_initcall(cpuinfo_regs_init); 325 326static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) 327{ 328 unsigned int cpu = smp_processor_id(); 329 u32 l1ip = CTR_L1IP(info->reg_ctr); 330 331 switch (l1ip) { 332 case ICACHE_POLICY_PIPT: 333 break; 334 case ICACHE_POLICY_VPIPT: 335 set_bit(ICACHEF_VPIPT, &__icache_flags); 336 break; 337 case ICACHE_POLICY_RESERVED: 338 case ICACHE_POLICY_VIPT: 339 /* Assume aliasing */ 340 set_bit(ICACHEF_ALIASING, &__icache_flags); 341 break; 342 } 343 344 pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu); 345} 346 347static void __cpuinfo_store_cpu(struct cpuinfo_arm64 *info) 348{ 349 info->reg_cntfrq = arch_timer_get_cntfrq(); 350 /* 351 * Use the effective value of the CTR_EL0 than the raw value 352 * exposed by the CPU. CTR_EL0.IDC field value must be interpreted 353 * with the CLIDR_EL1 fields to avoid triggering false warnings 354 * when there is a mismatch across the CPUs. Keep track of the 355 * effective value of the CTR_EL0 in our internal records for 356 * acurate sanity check and feature enablement. 357 */ 358 info->reg_ctr = read_cpuid_effective_cachetype(); 359 info->reg_dczid = read_cpuid(DCZID_EL0); 360 info->reg_midr = read_cpuid_id(); 361 info->reg_revidr = read_cpuid(REVIDR_EL1); 362 363 info->reg_id_aa64dfr0 = read_cpuid(ID_AA64DFR0_EL1); 364 info->reg_id_aa64dfr1 = read_cpuid(ID_AA64DFR1_EL1); 365 info->reg_id_aa64isar0 = read_cpuid(ID_AA64ISAR0_EL1); 366 info->reg_id_aa64isar1 = read_cpuid(ID_AA64ISAR1_EL1); 367 info->reg_id_aa64isar2 = read_cpuid(ID_AA64ISAR2_EL1); 368 info->reg_id_aa64mmfr0 = read_cpuid(ID_AA64MMFR0_EL1); 369 info->reg_id_aa64mmfr1 = read_cpuid(ID_AA64MMFR1_EL1); 370 info->reg_id_aa64mmfr2 = read_cpuid(ID_AA64MMFR2_EL1); 371 info->reg_id_aa64pfr0 = read_cpuid(ID_AA64PFR0_EL1); 372 info->reg_id_aa64pfr1 = read_cpuid(ID_AA64PFR1_EL1); 373 info->reg_id_aa64zfr0 = read_cpuid(ID_AA64ZFR0_EL1); 374 375 /* Update the 32bit ID registers only if AArch32 is implemented */ 376 if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) { 377 info->reg_id_dfr0 = read_cpuid(ID_DFR0_EL1); 378 info->reg_id_dfr1 = read_cpuid(ID_DFR1_EL1); 379 info->reg_id_isar0 = read_cpuid(ID_ISAR0_EL1); 380 info->reg_id_isar1 = read_cpuid(ID_ISAR1_EL1); 381 info->reg_id_isar2 = read_cpuid(ID_ISAR2_EL1); 382 info->reg_id_isar3 = read_cpuid(ID_ISAR3_EL1); 383 info->reg_id_isar4 = read_cpuid(ID_ISAR4_EL1); 384 info->reg_id_isar5 = read_cpuid(ID_ISAR5_EL1); 385 info->reg_id_isar6 = read_cpuid(ID_ISAR6_EL1); 386 info->reg_id_mmfr0 = read_cpuid(ID_MMFR0_EL1); 387 info->reg_id_mmfr1 = read_cpuid(ID_MMFR1_EL1); 388 info->reg_id_mmfr2 = read_cpuid(ID_MMFR2_EL1); 389 info->reg_id_mmfr3 = read_cpuid(ID_MMFR3_EL1); 390 info->reg_id_mmfr4 = read_cpuid(ID_MMFR4_EL1); 391 info->reg_id_mmfr5 = read_cpuid(ID_MMFR5_EL1); 392 info->reg_id_pfr0 = read_cpuid(ID_PFR0_EL1); 393 info->reg_id_pfr1 = read_cpuid(ID_PFR1_EL1); 394 info->reg_id_pfr2 = read_cpuid(ID_PFR2_EL1); 395 396 info->reg_mvfr0 = read_cpuid(MVFR0_EL1); 397 info->reg_mvfr1 = read_cpuid(MVFR1_EL1); 398 info->reg_mvfr2 = read_cpuid(MVFR2_EL1); 399 } 400 401 if (IS_ENABLED(CONFIG_ARM64_SVE) && id_aa64pfr0_sve(info->reg_id_aa64pfr0)) { 402 info->reg_zcr = read_zcr_features(); 403 } 404 405 cpuinfo_detect_icache_policy(info); 406} 407 408void cpuinfo_store_cpu(void) 409{ 410 struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data); 411 __cpuinfo_store_cpu(info); 412 update_cpu_features(smp_processor_id(), info, &boot_cpu_data); 413} 414 415void __init cpuinfo_store_boot_cpu(void) 416{ 417 struct cpuinfo_arm64 *info = &per_cpu(cpu_data, 0); 418 __cpuinfo_store_cpu(info); 419 420 boot_cpu_data = *info; 421 init_cpu_features(&boot_cpu_data); 422} 423