1/* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16#ifndef _BOOT_ROM_H_ 17#define _BOOT_ROM_H_ 18#include <hi_types.h> 19#include <hi_cipher.h> 20 21#define BOOTLOADER_FLASH_HEAD_ADDR 0x00400000 22 23/* This register is used internally and cannot be used externally. */ 24#define GLB_CTL_GP_REG0_REG (GLB_CTL_BASE + 0x10) 25#define GLB_CTL_GP_REG1_REG (GLB_CTL_BASE + 0x14) 26#define GLB_CTL_GP_REG2_REG (GLB_CTL_BASE + 0x18) 27#define GLB_CTL_GP_REG3_REG (GLB_CTL_BASE + 0x1C) 28#define PMU_CMU_CTL_GP_REG0_REG (PMU_CMU_CTL_BASE + 0x010) 29#define PMU_CMU_CTL_GP_REG1_REG (PMU_CMU_CTL_BASE + 0x014) 30#define PMU_CMU_CTL_GP_REG2_REG (PMU_CMU_CTL_BASE + 0x018) 31#define PMU_CMU_CTL_GP_REG3_REG (PMU_CMU_CTL_BASE + 0x01C) 32#define CLDO_CTL_GEN_REG0 (CLDO_CTL_RB_BASE + 0x10) 33#define CLDO_CTL_GEN_REG1 (CLDO_CTL_RB_BASE + 0x14) 34#define CLDO_CTL_GEN_REG2 (CLDO_CTL_RB_BASE + 0x18) 35#define CLDO_CTL_GEN_REG3 (CLDO_CTL_RB_BASE + 0x1C) 36 37/* heap module */ 38hi_void rom_boot_malloc_init(hi_u32 heap_start_addr, hi_u32 heap_end_addr, hi_u32 check_sum); 39hi_void *rom_boot_malloc(hi_u32 size); 40hi_u32 rom_boot_free(hi_void *addr); 41 42/* reset module */ 43#define RESET_DELAY_MS 3 44hi_void reset(hi_void); 45hi_void global_reset(hi_void); 46 47/* secure module */ 48HI_EXTERN hi_cipher_ecc_param g_brain_pool_p256r1_verify; 49 50/* flash driver module */ 51#define FEATURE_SUPPORT_FLASH_PROTECT 52 53#define flash_info_print(fmt, ...) 54#define SPI_QE_EN 0x02 /* QE Bit Enable */ 55#define SPI_QE_EN_MX 0x40 /* QE Bit Enable(temp for FPGA MX) */ 56 57#define SPI_CMD_WREN 0x06 /* Write Enable */ 58/* ----------------------------------------------------------------------------- */ 59#define SPI_CMD_SE_4K 0x20 /* 4KB sector Erase */ 60#define SPI_CMD_SE_32K 0x52 /* 32KB sector Erase */ 61#define SPI_CMD_SE 0xD8 /* 64KB Sector Erase */ 62#define SPI_CMD_CE1 0xC7 /* chip erase */ 63#define SPI_CMD_CE2 0x60 /* chip erase */ 64 65/* ----------------------------------------------------------------------------- */ 66#define SPI_CMD_WRSR1 0x01 /* Write Status Register */ 67 68#define SPI_CMD_WRSR2 0x31 /* Write Status Register-2 */ 69#define SPI_CMD_RDSR2 0x35 /* Read Status Register-2 */ 70 71#define SPI_CMD_WRSR3 0x11 /* Write Status Register-3 */ 72#define SPI_CMD_RDSR3 0x15 /* Read Status Register-3 */ 73 74#define SPI_CMD_RDID 0x9F /* Read Identification */ 75 76/* read status register. */ 77#define SPI_CMD_RDSR 0x05 78#define SPI_CMD_VSR_WREN 0x50 /* write volatile SR reg enable */ 79 80/* write status/configuration register. */ 81#define SPI_CMD_WRSRCR 0x01 82 83/* ----------------------------------------------------------------------------- */ 84#define SPI_CMD_SR_WIPN 0 /* Write in Progress */ 85#define SPI_CMD_SR_WIP 1 /* Write in Progress */ 86#define SPI_CMD_SR_WEL 2 /* Write Enable Latch */ 87 88#define SPI_SR_BIT_WIP (1 << 0) /* Write in Progress */ 89#define SPI_SR_BIT_WEL (1 << 1) /* Write Enable Latch */ 90 91#define FLASH_DMA_BUF_LEN 256 92#define FLASH_DMA_RAM_SIZE 1024 93#define HI_FLASH_DEFAULT_TYPE_NUM 8 94#define HI_FLASH_CHIP_ID_NUM 3 95#define HI_FLASH_CAPACITY_ID 2 96typedef struct { 97 hi_u32 cmd : 8; 98 hi_u32 iftype : 3; 99 hi_u32 dummy : 3; 100 hi_u32 size : 18; 101} spi_flash_operation; 102 103typedef enum { 104 HI_FLASH_SUPPORT_4K_ERASE = 0x1, /* Flash 4K erasing */ 105 HI_FLASH_SUPPORT_32K_ERASE = 0x2, /* Flash 32K erasing */ 106 HI_FLASH_SUPPORT_64K_ERASE = 0x4, /* Flash 64K erasing */ 107 HI_FLASH_SUPPORT_CHIP_ERASE = 0x8, /* Flash full-chip erasing */ 108 HI_FLASH_SUPPORT_AREA_LOCK_NV = 0x10, /* Non-volatile flash area protection */ 109 HI_FLASH_SUPPORT_AREA_LOCK_VOLATILE = 0x20, /* Flash volatile area protection */ 110 HI_FLASH_SUPPORT_INDIVIDUAL_LOCK = 0x40, /* Independent flash block protection */ 111 HI_FLASH_VLT_INFLUENCE_FREQ = 0x100, 112 HI_FLASH_SUPPORT_MASK = 0xFFFF, /* Mask */ 113} hi_spi_flash_chip_attribute; 114 115typedef struct { 116 hi_char *chip_name; 117 hi_u8 chip_id[HI_FLASH_CHIP_ID_NUM]; 118 hi_u8 freq_read; 119 hi_u8 freq_lowpower; 120 hi_u8 freq_hpm; 121 hi_u16 chip_attribute; 122} hi_spi_flash_basic_info; 123 124#define HI_FLASH_SUPPORT_CHIPS (HI_FLASH_SUPPORT_4K_ERASE | \ 125 HI_FLASH_SUPPORT_64K_ERASE | \ 126 HI_FLASH_SUPPORT_CHIP_ERASE | \ 127 HI_FLASH_SUPPORT_AREA_LOCK_NV | \ 128 HI_FLASH_SUPPORT_AREA_LOCK_VOLATILE) 129#define HI_FLASH_SUPPORT_DEFAULT (HI_FLASH_SUPPORT_4K_ERASE | \ 130 HI_FLASH_SUPPORT_64K_ERASE | \ 131 HI_FLASH_SUPPORT_CHIP_ERASE) 132 133#define PRODUCT_CFG_FLASH_BLOCK_SIZE 0x1000 134/*****************************************************************************/ 135#define HISFC300_DMA_MAX_SIZE 2048 136#define HISFC300_DMA_MAX_MASK 0x7FF 137 138/*****************************************************************************/ 139#define HISFC300_REG_BUF_SIZE 64 140#define HISFC300_REG_BUF_MASK 0x3F 141 142#define HISFC300_BUS_CONFIG2 0x0204 143#define HISFC300_BUS_BASE_ADDR_CS1 0x0218 144#define HISFC300_BUS_ALIAS_ADDR 0x021C 145#define HISFC300_BUS_ALIAS_CS 0x0220 146#define HISFC300_CMD_DATABUF64 0x04FC 147 148#define SFC_REG_BASE_ADDRESS HI_SFC_REG_BASE 149#define SFC_BUFFER_BASE_ADDRESS 0x400000 150 151#define SFC_REG_GLOBAL_CONFIG 0x0100 152#define SFC_REG_GLOBAL_CONFIG_ADDR_MODE_4B (1 << 2) 153#define SFC_REG_TIMING 0x0110 154#define SFC_REG_GLOBAL_CONFIG_WP_ENABLE (1 << 1) 155#define sfc_timing_tshsl(_n) ((_n) & 0xF) 156#define sfc_timing_tshwl(_n) (((_n) & 0xF) << 4) 157#define sfc_timing_tcss(_n) (((_n) & 0x7) << 8) 158#define sfc_timing_tcsh(_n) (((_n) & 0x7) << 12) 159#define sfc_timing_trpd(_n) (((_n) & 0xFFF) << 16) 160#define SFC_REG_INT_RAW_STATUS 0x0120 /* Raw interrupt status register */ 161#define SFC_REG_INT_RAW_STATUS_DMA_DONE (1 << 1) 162#define SFC_REG_INT_STATUS 0x0124 163#define SFC_REG_INT_MASK 0x0128 164#define SFC_REG_INT_CLEAR 0x012C 165#define SFC_REG_INT_CLEAR_DMA_DONE (1 << 1) 166#define SFC_REG_VERSION 0x01F8 167#define SFC_REG_VERSION_SEL 0x01FC 168#define SFC_REG_BUS_CONFIG1 0x0200 169#define SFC_REG_BUS_CONFIG1_MASK_RD 0x8000ffff 170#define SFC_REG_BUS_CONFIG1_MASK_WT 0x7fff0000 171#define sfc_bus_config1_wr_ins(_n) (((_n) & 0xFF) << 22) 172#define sfc_bus_config1_rd_ins(_n) (((_n) & 0xFF) << 8) 173#define sfc_bus_config1_rd_prefetch_cnt(_n) (((_n) & 0x3) << 6) 174#define sfc_bus_config1_rd_dummy_bytes(_n) (((_n) & 0x7) << 3) 175#define sfc_bus_config1_rd_mem_if_type(_n) ((_n) & 0x7) 176#define SFC_BUS_CONFIG1_RD_ENABLE ((hi_u32)1 << 31) 177 178#define SFC_REG_BUS_FLASH_SIZE 0x0210 179#define SFC_REG_BUS_BASE_ADDR_CS0 0x0214 180#define SFC_REG_BUS_BASE_ADDR_CS1 0x0218 181 182#define SFC_REG_BUS_DMA_CTRL 0X0240 183#define SFC_BUS_DMA_CTRL_START (1 << 0) 184#define sfc_bus_dma_ctrl_read(_dir) ((_dir) << 1) 185#define sfc_bus_dma_ctrl_cs(_cs) (((_cs) & 0x01) << 4) 186#define SFC_REG_BUS_DMA_MEM_SADDR 0X0244 /* DMA DDR start address R */ 187#define SFC_REG_BUS_DMA_FLASH_SADDR 0X0248 188#define SFC_REG_BUS_DMA_LEN 0x024C 189#define SFC_REG_BUS_DMA_AHB_CTRL 0X0250 190#define SFC_BUS_DMA_AHB_CTRL_INCR4_EN (1 << 0) 191#define SFC_BUS_DMA_AHB_CTRL_INCR8_EN (1 << 1) 192#define SFC_BUS_DMA_AHB_CTRL_INCR16_EN (1 << 2) 193 194#define SFC_REG_CMD_CONFIG 0x0300 195#define sfc_cmd_config_mem_if_type(_n) (((_n) & 0x07) << 17) 196#define sfc_cmd_config_data_cnt(_n) ((((_n) - 1) & HISFC300_REG_BUF_MASK) << 9) 197#define SFC_CMD_CONFIG_RW (1 << 8) 198#define SFC_CMD_CONFIG_DATA_EN (1 << 7) 199#define sfc_cmd_config_dummy_byte_cnt(_n) (((_n) & 0x07) << 4) 200#define SFC_CMD_CONFIG_ADDR_EN (1 << 3) 201#define SFC_CMD_CONFIG_SEL_CS (0x01 << 1) 202#define SFC_CMD_CONFIG_START (1 << 0) 203#define SFC_REG_CMD_INS 0x0308 204 205#define SFC_REG_CMD_ADDR 0x030C 206#define SFC_CMD_ADDR_MASK 0x3FFFFFFF 207#define SFC_REG_CMD_DATABUF1 0x0400 208 209#define SPI_SR3_DRV_MASK 0x3 210 211#define SFC_ERASE_OPT_MAX_NUM 4 212 213typedef enum { 214 SPI_SR3_DRV_100PCT = 0, 215 SPI_SR3_DRV_75PCT, 216 SPI_SR3_DRV_50PCT, 217 SPI_SR3_DRV_25PCT, 218 SPI_SR3_DRV_MAX, 219} hi_flash_drv_strength; 220 221#define SFC_CMD_WRITE (0 << 8) 222#define SFC_CMD_READ (1 << 8) 223 224typedef enum { 225 HI_FLASH_CHECK_PARAM_OPT_READ, 226 HI_FLASH_CHECK_PARAM_OPT_WRITE, 227 HI_FLASH_CHECK_PARAM_OPT_ERASE, 228} hi_flash_check_param_opt; 229 230typedef struct spi_flash_ctrl { 231 hi_u32 is_inited; 232 hi_spi_flash_basic_info basic_info; 233 spi_flash_operation opt_read; 234 spi_flash_operation opt_write; 235 spi_flash_operation array_opt_erase[SFC_ERASE_OPT_MAX_NUM]; 236 hi_u32 chip_size; 237 hi_u32 erase_size; 238 hi_u32 dma_ram_size; 239 hi_u8 *dma_ram_buffer; 240 hi_u8 *back_up_buf; 241 hi_u32(*read)(struct spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, 242 hi_u32 read_size, hi_void *ram_addr, hi_bool is_crash); 243 hi_u32(*write)(struct spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, 244 hi_u32 write_size, hi_void *ram_addr, hi_bool is_crash); 245 hi_u32(*erase)(struct spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, 246 hi_u32 erase_size, hi_bool is_crash); 247 hi_u32 mutex_handle; 248 hi_pvoid usr_data; 249} hi_spi_flash_ctrl; 250 251/*****************************************************************************/ 252#define hisfc_read(_reg) \ 253 hi_reg_read_val32(SFC_REG_BASE_ADDRESS + (_reg)) 254 255#define hisfc_write(_reg, _value) \ 256 hi_reg_write(SFC_REG_BASE_ADDRESS + (_reg), (_value)) 257 258 259HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_fast_quad_out_read; 260HI_EXTERN HI_CONST spi_flash_operation g_spi_opt_fast_quad_eb_out_read; 261 262HI_EXTERN HI_CONST hi_spi_flash_basic_info g_flash_default_info_tbl[]; 263 264hi_u32 spi_flash_read_chip_id(hi_u8 *chip_id, hi_u8 chip_id_len); 265hi_u32 spi_flash_configure_driver_strength(hi_flash_drv_strength drv_strength); 266 267hi_u32 spif_map_chipsize(hi_u32 chip_size); 268hi_u32 spif_dma_read(hi_spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, hi_u32 read_size, hi_void *ram_addr, 269 hi_bool is_crash); 270hi_u32 spif_reg_erase(hi_spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, hi_u32 erase_size, hi_bool is_crash); 271hi_u32 spif_dma_write(hi_spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, hi_u32 write_size, hi_void *ram_addr, 272 hi_bool is_crash); 273hi_u32 spi_flash_read_reg(hi_u8 cmd, hi_u8 *data, hi_u8 data_len); 274hi_u32 spi_flash_write_reg(hi_u8 cmd, const hi_u8 *data, hi_u8 data_len); 275hi_void spif_config(const spi_flash_operation *spi_operation, hi_u8 cmd, hi_bool read); 276hi_u32 spi_flash_enable_quad_mode_mx(hi_void); 277hi_u32 spi_flash_enable_quad_mode(hi_void); 278hi_void spif_wait_config_start(hi_void); 279hi_u32 spif_write_enable(hi_bool is_crash); 280hi_u32 spif_wait_ready(hi_bool is_crash, hi_u8 val, hi_u8 bit_mask); 281 282hi_u32 spi_flash_basic_info_probe(hi_spi_flash_ctrl *spif_ctrl, hi_u8 *chip_id, 283 hi_u8 id_len, hi_spi_flash_basic_info *spi_info_tbl, hi_u32 tbl_size); 284hi_u32 flash_write_prv(hi_spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, const hi_u8 *ram_addr, hi_u32 size, 285 hi_bool do_erase); 286hi_u32 flash_erase_prv(hi_spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, hi_u32 size); 287hi_u32 flash_read_prv(hi_spi_flash_ctrl *spif_ctrl, hi_u32 flash_addr, hi_u8 *data, hi_u32 size); 288hi_u32 spi_flash_get_size(const hi_u8 *chip_id); 289hi_u32 sfc_check_para(const hi_spi_flash_ctrl *spif_ctrl, hi_u32 addr, hi_u32 size, hi_flash_check_param_opt opt); 290hi_u32 flash_protect_set_protect(hi_u8 cmp_bp, hi_bool is_volatile); 291 292typedef hi_u32 (*flash_init_func)(hi_void); 293typedef hi_u32 (*flash_read_func)(hi_u32 flash_addr, hi_u32 flash_read_size, hi_u8 *p_flash_read_data); 294typedef hi_u32 (*flash_write_func)(hi_u32 flash_addr, hi_u32 flash_write_size, 295 const hi_u8 *p_flash_write_data, hi_bool do_erase); 296typedef hi_u32 (*flash_erase_func)(hi_u32 flash_addr, hi_u32 flash_erase_size); 297 298typedef struct { 299 flash_init_func init; 300 flash_read_func read; 301 flash_write_func write; 302 flash_erase_func erase; 303} hi_flash_cmd_func; 304HI_EXTERN hi_flash_cmd_func g_flash_cmd_funcs; 305 306hi_u32 hi_cmd_regist_flash_cmd(const hi_flash_cmd_func *funcs); 307 308#endif 309