1/*
2 * Copyright (c) 2020-2021 Huawei Device Co., Ltd.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 *     http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16#ifndef _SOC_H
17#define _SOC_H
18#include "soc_common.h"
19
20/*
21 * Get the response interrupt number via mcause.
22 * id = mcause & MCAUSE_INT_ID_MASK
23 */
24#define MSIP                                          0x2000000
25#define MTIMERCMP                                     0x2004000
26#define MTIMER                                        0x200BFF8
27#define CLOCK_CONTRAL_REG                             0x10008000
28
29/* interrupt base addr : 0xc000000 + 4 * interrupt ID
30 * [2:0]   priority
31 * [31:3]  reserved
32 */
33#define PLIC_PRIO_BASE                                 0xC000000
34#define PLIC_PEND_BASE                                 0xC001000 /* interrupt 0-31 */
35#define PLIC_PEND_REG2                                 0xC001004 /* interrupt 32-52 */.
36#define PLIC_ENABLE_BASE                               0xC002000 /* interrupt 0-31 */
37#define PLIC_ENABLE_REG2                               0xC002004 /* interrupt 32-52 */
38#define PLIC_REG_BASE                                  0xC200000
39
40#define UART0_BASE                                     0x10000000
41
42#define UART0_CLK_FREQ                                 0x32000000
43#define UART0_BAUDRAT                                  115200
44
45#define RISCV_SYS_MAX_IRQ                              11
46#define RISCV_WDOGCMP_IRQ                              (RISCV_SYS_MAX_IRQ + 1)
47#define RISCV_RTCCMP_IRQ                               (RISCV_SYS_MAX_IRQ + 2)
48#define RISCV_UART0_IRQ                                (RISCV_SYS_MAX_IRQ + 3)
49
50#define RISCV_PLIC_VECTOR_CNT                          53
51
52#endif
53