1d6aed566Sopenharmony_ci/* 2d6aed566Sopenharmony_ci * Copyright (c) 2020-2021 Huawei Device Co., Ltd. 3d6aed566Sopenharmony_ci * Licensed under the Apache License, Version 2.0 (the "License"); 4d6aed566Sopenharmony_ci * you may not use this file except in compliance with the License. 5d6aed566Sopenharmony_ci * You may obtain a copy of the License at 6d6aed566Sopenharmony_ci * 7d6aed566Sopenharmony_ci * http://www.apache.org/licenses/LICENSE-2.0 8d6aed566Sopenharmony_ci * 9d6aed566Sopenharmony_ci * Unless required by applicable law or agreed to in writing, software 10d6aed566Sopenharmony_ci * distributed under the License is distributed on an "AS IS" BASIS, 11d6aed566Sopenharmony_ci * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12d6aed566Sopenharmony_ci * See the License for the specific language governing permissions and 13d6aed566Sopenharmony_ci * limitations under the License. 14d6aed566Sopenharmony_ci */ 15d6aed566Sopenharmony_ci 16d6aed566Sopenharmony_ci#ifndef _SOC_H 17d6aed566Sopenharmony_ci#define _SOC_H 18d6aed566Sopenharmony_ci#include "soc_common.h" 19d6aed566Sopenharmony_ci 20d6aed566Sopenharmony_ci/* 21d6aed566Sopenharmony_ci * Get the response interrupt number via mcause. 22d6aed566Sopenharmony_ci * id = mcause & MCAUSE_INT_ID_MASK 23d6aed566Sopenharmony_ci */ 24d6aed566Sopenharmony_ci#define MSIP 0x2000000 25d6aed566Sopenharmony_ci#define MTIMERCMP 0x2004000 26d6aed566Sopenharmony_ci#define MTIMER 0x200BFF8 27d6aed566Sopenharmony_ci#define CLOCK_CONTRAL_REG 0x10008000 28d6aed566Sopenharmony_ci 29d6aed566Sopenharmony_ci/* interrupt base addr : 0xc000000 + 4 * interrupt ID 30d6aed566Sopenharmony_ci * [2:0] priority 31d6aed566Sopenharmony_ci * [31:3] reserved 32d6aed566Sopenharmony_ci */ 33d6aed566Sopenharmony_ci#define PLIC_PRIO_BASE 0xC000000 34d6aed566Sopenharmony_ci#define PLIC_PEND_BASE 0xC001000 /* interrupt 0-31 */ 35d6aed566Sopenharmony_ci#define PLIC_PEND_REG2 0xC001004 /* interrupt 32-52 */. 36d6aed566Sopenharmony_ci#define PLIC_ENABLE_BASE 0xC002000 /* interrupt 0-31 */ 37d6aed566Sopenharmony_ci#define PLIC_ENABLE_REG2 0xC002004 /* interrupt 32-52 */ 38d6aed566Sopenharmony_ci#define PLIC_REG_BASE 0xC200000 39d6aed566Sopenharmony_ci 40d6aed566Sopenharmony_ci#define UART0_BASE 0x10000000 41d6aed566Sopenharmony_ci 42d6aed566Sopenharmony_ci#define UART0_CLK_FREQ 0x32000000 43d6aed566Sopenharmony_ci#define UART0_BAUDRAT 115200 44d6aed566Sopenharmony_ci 45d6aed566Sopenharmony_ci#define RISCV_SYS_MAX_IRQ 11 46d6aed566Sopenharmony_ci#define RISCV_WDOGCMP_IRQ (RISCV_SYS_MAX_IRQ + 1) 47d6aed566Sopenharmony_ci#define RISCV_RTCCMP_IRQ (RISCV_SYS_MAX_IRQ + 2) 48d6aed566Sopenharmony_ci#define RISCV_UART0_IRQ (RISCV_SYS_MAX_IRQ + 3) 49d6aed566Sopenharmony_ci 50d6aed566Sopenharmony_ci#define RISCV_PLIC_VECTOR_CNT 53 51d6aed566Sopenharmony_ci 52d6aed566Sopenharmony_ci#endif 53