1/*
2 * Copyright (c) 2020-2021 Huawei Device Co., Ltd.
3 * Licensed under the Apache License, Version 2.0 (the "License");
4 * you may not use this file except in compliance with the License.
5 * You may obtain a copy of the License at
6 *
7 *     http://www.apache.org/licenses/LICENSE-2.0
8 *
9 * Unless required by applicable law or agreed to in writing, software
10 * distributed under the License is distributed on an "AS IS" BASIS,
11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12 * See the License for the specific language governing permissions and
13 * limitations under the License.
14 */
15
16#ifndef _UART_H
17#define _UART_H
18
19#include "los_compiler.h"
20#include "los_event.h"
21#include "los_reg.h"
22#include "soc.h"
23
24#define RISCV_UART0_Rx_IRQn  (RISCV_SYS_MAX_IRQ + 10)
25
26// the UART control registers.
27// some have different meanings for read vs write.
28// see http://byterunner.com/16550.html
29#define UART_RHR_OFFSET      0 /* receive holding register (for input bytes) */
30#define UART_THR_OFFSET      0 /* transmit holding register (for output bytes) */
31#define UART_DLL_OFFSET      0 /* Divisor Latch (Least Significant Byte) Register (LSB) */
32#define UART_IER_OFFSET      1 /* interrupt enable register */
33#define UART_DLM_OFFSET      1 /* Divisor Latch (Most Significant Byte) Register (MSB) */
34#define UART_FCR_OFFSET      2 /* FIFO control register */
35#define UART_ISR_OFFSET      2 /* interrupt status register */
36#define UART_LCR_OFFSET      3 /* line control register */
37#define UART_LSR_OFFSET      5 /* line status register */
38
39#define UART_LCR_8N1         0x03 /* useful defaults for LCR */
40#define UART_LCR_DLAB        0x80 /* Divisor latch access bit */
41
42#define UART_IER_RDI         0x01 /* Enable receiver data interrupt */
43#define UART_IER_THRI        0x02 /* Enable Transmitter holding register int. */
44
45#define UART_FCR_FIFO_EN     0x01 /* FIFO Enable */
46#define UART_FCR_RXSR        0x02 /* Receiver soft reset */
47#define UART_FCR_TXSR        0x04 /* Transmitter soft reset */
48
49#define UART_LSR_DR          0x01 /* Receiver data ready */
50#define UART_LSR_THRE        0x20 /* Transmit-hold-register empty */
51
52#define ReadUartReg(reg)     GET_UINT8((UART0_BASE) + (reg))
53#define WriteUartReg(reg, v) WRITE_UINT8((v), (UART0_BASE) + (reg))
54
55#ifdef __cplusplus
56#if __cplusplus
57extern "C" {
58#endif
59#endif
60
61extern INT32 UartPutc(INT32 c, VOID *file);
62extern INT32 UartOut(INT32 c, VOID *file);
63
64extern VOID UartInit(VOID);
65extern INT32 UartGetc(VOID);
66extern VOID Uart0RxIrqRegister(VOID);
67
68extern EVENT_CB_S g_shellInputEvent;
69
70#ifdef __cplusplus
71#if __cplusplus
72}
73#endif /* __cplusplus */
74#endif /* __cplusplus */
75#endif
76