1/* 2 * Copyright (c) 2013-2019 Huawei Technologies Co., Ltd. All rights reserved. 3 * Copyright (c) 2020-2021 Huawei Device Co., Ltd. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without modification, 6 * are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, this list of 9 * conditions and the following disclaimer. 10 * 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this list 12 * of conditions and the following disclaimer in the documentation and/or other materials 13 * provided with the distribution. 14 * 15 * 3. Neither the name of the copyright holder nor the names of its contributors may be used 16 * to endorse or promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 21 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 23 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 24 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 25 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 26 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 27 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 28 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 29 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32#ifndef _ST_CONFIG_H 33#define _ST_CONFIG_H 34 35#define IRQn_Type int 36 37#define __CM4_REV 0x0001 38#define __NVIC_PRIO_BITS 4 39#define __MPU_PRESENT 1 40#define __Vendor_SysTickConfig 0 41#define __FPU_PRESENT 1 42 43#define SysTick_IRQn (-1) 44#define PendSV_IRQn (-2) 45#define NonMaskableInt_IRQn (-14) 46#define MemoryManagement_IRQn (-12) 47#define BusFault_IRQn (-11) 48#define UsageFault_IRQn (-10) 49#define SVCall_IRQn (-5) 50 51#define Uart0_Rx_IRQn 0 52 53#define SYSCLK_FREQ 25000000 54 55#define UART0_BASE 0x40004000 56#define UART1_BASE 0x40005000 57#define UART2_BASE 0x40006000 58#define UART3_BASE 0x40007000 59#define UART4_BASE 0x40009000 60 61#define UART0_CLK_FREQ SYSCLK_FREQ 62#define UART0_BAUDRAT 115200 63 64#define WATCHDOG_BASE 0x40008000 65#define GPIO_BASE(no) (0x40010000 + (unsigned int)(no) * 0x1000) /* no: 0 ~ 3 */ 66#define TIMER_BASE(no) (0x40000000 + (unsigned int)(no) * 0x1000) 67 68#endif 69 70#include "core_cm4.h" 71