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Searched refs:write_mask (Results 1 - 25 of 158) sorted by relevance

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/third_party/mesa3d/src/compiler/nir/
H A Dnir_lower_vec_to_movs.c74 mov->dest.write_mask = (1u << start_idx); in insert_mov()
80 if (!(vec->dest.write_mask & (1 << i))) in insert_mov()
86 mov->dest.write_mask |= (1 << i); in insert_mov()
91 unsigned channels_handled = mov->dest.write_mask; in insert_mov()
101 mov->dest.write_mask &= ~(1 << i); in insert_mov()
107 if (mov->dest.write_mask) { in insert_mov()
193 unsigned write_mask = 0; in try_coalesce() local
195 if (!(vec->dest.write_mask & (1 << i))) in try_coalesce()
202 write_mask |= 1 << i; in try_coalesce()
207 if (data->cb && !data->cb(&src_alu->instr, write_mask, dat in try_coalesce()
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H A Dnir_opt_undef.c155 unsigned write_mask = nir_intrinsic_write_mask(intrin); in opt_undef_store() local
158 if (!(write_mask & undef_mask)) in opt_undef_store()
161 write_mask &= ~undef_mask; in opt_undef_store()
162 if (!write_mask) in opt_undef_store()
165 nir_intrinsic_set_write_mask(intrin, write_mask); in opt_undef_store()
H A Dnir_lower_regs_to_ssa.c119 unsigned write_mask = alu->dest.write_mask; in rewrite_alu_instr() local
120 if (write_mask == (1 << reg->num_components) - 1) { in rewrite_alu_instr()
144 if (write_mask & (1 << index)) in rewrite_alu_instr()
167 if (!((write_mask >> index) & 1)) in rewrite_alu_instr()
179 alu->dest.write_mask = (1 << num_components) - 1; in rewrite_alu_instr()
193 if (write_mask & (1 << i)) { in rewrite_alu_instr()
H A Dnir_opt_combine_stores.c55 nir_component_mask_t write_mask; member
104 combo->write_mask = 0; in free_combined_store()
118 if ((combo->write_mask & nir_intrinsic_write_mask(combo->latest)) == in combine_stores()
119 combo->write_mask) in combine_stores()
132 if (combo->write_mask & (1 << i)) { in combine_stores()
165 nir_intrinsic_set_write_mask(store, combo->write_mask); in combine_stores()
262 combo->write_mask |= vec_mask; in update_combined_store()
H A Dnir_opt_comparison_pre.c174 mov_add->dest.write_mask = orig_add->dest.write_mask; in rewrite_compare_instruction()
183 mov_cmp->dest.write_mask = orig_cmp->dest.write_mask; in rewrite_compare_instruction()
H A Dnir_opt_shrink_stores.c83 unsigned write_mask = nir_intrinsic_write_mask(instr); in opt_shrink_store_instr() local
84 unsigned last_bit = util_last_bit(write_mask); in opt_shrink_store_instr()
/third_party/mesa3d/src/gallium/drivers/freedreno/a2xx/
H A Dir2_cp.c143 unsigned write_mask = 0; in cp_export() local
156 if (write_mask & instr->alu.write_mask) { in cp_export()
161 write_mask |= instr->alu.write_mask; in cp_export()
166 if (instr->alu.write_mask & 1 << k) { in cp_export()
172 x += !!(instr->alu.write_mask & 1 << i); in cp_export()
206 p->alu.write_mask = 0; in cp_export()
227 c[i]->alu.write_mask |= (1 << i); in cp_export()
H A Dir2_nir.c343 instr->alu.write_mask = (1 << ncomp) - 1; in instr_create_alu()
351 instr_create_alu_reg(struct ir2_context *ctx, nir_op opcode, uint8_t write_mask, in instr_create_alu_reg() argument
358 reg->ncomp = MAX2(reg->ncomp, util_logbase2(write_mask) + 1); in instr_create_alu_reg()
360 instr = instr_create_alu(ctx, opcode, util_bitcount(write_mask)); in instr_create_alu_reg()
361 instr->alu.write_mask = write_mask; in instr_create_alu_reg()
418 ncomp += !!(alu->dest.write_mask & 1 << i); in emit_alu()
424 instr->alu.write_mask = alu->dest.write_mask; in emit_alu()
432 if (!(alu->dest.write_mask in emit_alu()
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/third_party/mesa3d/src/compiler/glsl/
H A Dopt_constant_propagation.cpp53 acp_entry(ir_variable *var, unsigned write_mask, ir_constant *constant) in acp_entry() argument
58 this->write_mask = write_mask; in acp_entry()
60 this->initial_values = write_mask; in acp_entry()
66 this->write_mask = src->write_mask; in acp_entry()
73 unsigned write_mask; member in __anon7204::acp_entry
106 void kill(ir_variable *ir, unsigned write_mask);
190 if (entry->var == deref->var && entry->write_mask & (1 << channel)) { in constant_propagation()
287 unsigned kill_mask = ir->write_mask; in visit_leave()
450 kill(ir_variable *var, unsigned write_mask) kill() argument
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H A Dopt_dead_code_local.cpp57 this->unused = ir->write_mask; in assignment_entry()
207 ir->write_mask); in process_assignment()
218 int remove = entry->unused & ir->write_mask; in process_assignment()
222 entry->ir->write_mask, in process_assignment()
223 remove, entry->ir->write_mask & ~remove); in process_assignment()
234 entry->ir->write_mask &= ~remove; in process_assignment()
236 if (entry->ir->write_mask == 0) { in process_assignment()
243 * write_mask. in process_assignment()
250 if ((entry->ir->write_mask | remove) & (1 << i)) { in process_assignment()
H A Dopt_copy_propagation_elements.cpp95 void erase(ir_variable *var, unsigned write_mask) in erase() argument
103 if ((write_mask & (1 << i)) == 0) in erase()
137 void write_elements(ir_variable *lhs, ir_variable *rhs, unsigned write_mask, int swizzle[4]) in write_elements() argument
143 if ((write_mask & (1 << i)) == 0) in write_elements()
263 kill_entry(ir_variable *var, int write_mask) in kill_entry() argument
266 this->write_mask = write_mask; in kill_entry()
270 unsigned int write_mask; member in __anon7206::kill_entry
379 k = new(this->lin_ctx) kill_entry(var, ir->write_mask); in visit_leave()
641 state->erase(k->var, k->write_mask); in kill()
715 int write_mask = ir->write_mask; add_copy() local
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/third_party/mesa3d/src/gallium/auxiliary/tgsi/
H A Dtgsi_util.c113 uint8_t write_mask, in tgsi_util_get_src_usage_mask()
197 read_mask = write_mask & TGSI_WRITEMASK_YZ ? in tgsi_util_get_src_usage_mask()
203 read_mask = write_mask & TGSI_WRITEMASK_XYZ ? TGSI_WRITEMASK_X : 0; in tgsi_util_get_src_usage_mask()
215 read_mask = write_mask; in tgsi_util_get_src_usage_mask()
218 (write_mask & TGSI_WRITEMASK_XY ? TGSI_WRITEMASK_X : 0) | in tgsi_util_get_src_usage_mask()
219 (write_mask & TGSI_WRITEMASK_ZW ? TGSI_WRITEMASK_Z : 0); in tgsi_util_get_src_usage_mask()
225 read_mask = write_mask; in tgsi_util_get_src_usage_mask()
346 read_mask = write_mask; in tgsi_util_get_src_usage_mask()
356 read_mask = write_mask; in tgsi_util_get_src_usage_mask()
111 tgsi_util_get_src_usage_mask(enum tgsi_opcode opcode, unsigned src_idx, uint8_t write_mask, uint8_t swizzle_x, uint8_t swizzle_y, uint8_t swizzle_z, uint8_t swizzle_w, enum tgsi_texture_type tex_target, enum tgsi_texture_type mem_target) tgsi_util_get_src_usage_mask() argument
/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_shader_gs.cpp86 auto write_mask = nir_intrinsic_write_mask(instr); in process_store_output() local
87 ShaderOutput output(driver_location, name, write_mask); in process_store_output()
101 auto write_mask = nir_intrinsic_write_mask(instr); in process_store_output() local
102 m_cc_dist_mask |= write_mask << (4 * (location - VARYING_SLOT_CLIP_DIST0)); in process_store_output()
103 m_clip_dist_write |= write_mask << (4 * (location - VARYING_SLOT_CLIP_DIST0)); in process_store_output()
256 uint32_t write_mask = nir_intrinsic_write_mask(instr);
261 src_swz[i] = (1 << i) & (write_mask << shift) ? i - shift: 7;
271 if (!(write_mask & (1 << i)))
291 if ((write_mask & (1 << i)) && (out_value[i]->chan() != i)) {
H A Dsfn_shader_vs.cpp195 uint32_t write_mask = 0; in emit_varying_pos() local
197 write_mask = nir_intrinsic_write_mask(&intr) << store_info.frac; in emit_varying_pos()
201 swizzle[i] = ((1 << i) & write_mask) ? i - store_info.frac : 7; in emit_varying_pos()
242 m_cc_dist_mask |= write_mask << (4 * (store_info.location - VARYING_SLOT_CLIP_DIST0)); in emit_varying_pos()
243 m_clip_dist_write |= write_mask << (4 * (store_info.location - VARYING_SLOT_CLIP_DIST0)); in emit_varying_pos()
267 int write_mask = nir_intrinsic_write_mask(&intr) << store_info.frac; in emit_varying_param() local
270 swizzle[i] = ((1 << i) & write_mask) ? i - store_info.frac : 7; in emit_varying_param()
272 Pin pin = util_bitcount(write_mask) > 1 ? pin_group: pin_free; in emit_varying_param()
429 auto write_mask = nir_intrinsic_write_mask(intr); in do_scan_instruction() local
432 write_mask in do_scan_instruction()
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H A Dsfn_shader_tess.cpp207 auto write_mask = nir_intrinsic_write_mask(intr); in do_scan_instruction() local
210 write_mask = 4; in do_scan_instruction()
212 ShaderOutput output(driver_location, name, write_mask); in do_scan_instruction()
/third_party/mesa3d/src/gallium/drivers/i915/
H A Di915_fpc_optimize.c152 is_unswizzled(struct i915_full_src_register *r, unsigned write_mask) in is_unswizzled() argument
154 if (write_mask & TGSI_WRITEMASK_X && r->Register.SwizzleX != TGSI_SWIZZLE_X) in is_unswizzled()
156 if (write_mask & TGSI_WRITEMASK_Y && r->Register.SwizzleY != TGSI_SWIZZLE_Y) in is_unswizzled()
158 if (write_mask & TGSI_WRITEMASK_Z && r->Register.SwizzleZ != TGSI_SWIZZLE_Z) in is_unswizzled()
160 if (write_mask & TGSI_WRITEMASK_W && r->Register.SwizzleW != TGSI_SWIZZLE_W) in is_unswizzled()
188 unsigned write_mask, unsigned neutral) in set_neutral_element_swizzle()
190 if (write_mask & TGSI_WRITEMASK_X) in set_neutral_element_swizzle()
195 if (write_mask & TGSI_WRITEMASK_Y) in set_neutral_element_swizzle()
200 if (write_mask & TGSI_WRITEMASK_Z) in set_neutral_element_swizzle()
205 if (write_mask in set_neutral_element_swizzle()
187 set_neutral_element_swizzle(struct i915_full_src_register *r, unsigned write_mask, unsigned neutral) set_neutral_element_swizzle() argument
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/third_party/mesa3d/src/gallium/drivers/lima/ir/pp/
H A Dppir.h271 unsigned write_mask : 4; member
678 if ((dest->write_mask & 0x3) == 0x3 || in ppir_target_is_scalar()
679 (dest->write_mask & 0x5) == 0x5 || in ppir_target_is_scalar()
680 (dest->write_mask & 0x9) == 0x9 || in ppir_target_is_scalar()
681 (dest->write_mask & 0x6) == 0x6 || in ppir_target_is_scalar()
682 (dest->write_mask & 0xa) == 0xa || in ppir_target_is_scalar()
683 (dest->write_mask & 0xc) == 0xc) in ppir_target_is_scalar()
/third_party/mesa3d/src/amd/common/
H A Dac_nir_lower_tess_io_to_mem.c256 unsigned write_mask = nir_intrinsic_write_mask(intrin); in lower_ls_output_store() local
259 nir_store_shared(b, intrin->src[0].ssa, off, .write_mask = write_mask, in lower_ls_output_store()
431 unsigned write_mask = nir_intrinsic_write_mask(intrin); in lower_hs_output_store() local
445 nir_store_buffer_amd(b, store_val, hs_ring_tess_offchip, vmem_off, offchip_offset, .write_mask = write_mask, .memory_modes = nir_var_shader_out); in lower_hs_output_store()
456 nir_store_shared(b, store_val, lds_off, .write_mask = write_mask, in lower_hs_output_store()
H A Dac_nir_lower_esgs_io_to_mem.c161 unsigned write_mask = nir_intrinsic_write_mask(intrin); in lower_es_output_store() local
172 write_mask, true, true); in lower_es_output_store()
177 nir_build_store_shared(b, intrin->src[0].ssa, off, .write_mask = write_mask, in lower_es_output_store()
/third_party/mesa3d/src/gallium/auxiliary/nir/
H A Dnir_to_tgsi.c238 ntt_64bit_write_mask(unsigned write_mask) in ntt_64bit_write_mask() argument
240 return ((write_mask & 1) ? 0x3 : 0) | ((write_mask & 2) ? 0xc : 0); in ntt_64bit_write_mask()
726 unsigned write_mask; in ntt_output_decl() local
728 write_mask = nir_intrinsic_write_mask(instr); in ntt_output_decl()
730 write_mask = ((1 << instr->num_components) - 1) << *frac; in ntt_output_decl()
733 write_mask = ntt_64bit_write_mask(write_mask); in ntt_output_decl()
735 write_mask = write_mask << in ntt_output_decl()
1074 uint32_t write_mask = BITFIELD_MASK(nir_reg->num_components); ntt_setup_registers() local
1210 ntt_swizzle_for_write_mask(struct ureg_src src, uint32_t write_mask) ntt_swizzle_for_write_mask() argument
2023 unsigned write_mask = nir_intrinsic_write_mask(instr); ntt_emit_mem() local
2332 uint32_t write_mask = BITSET_MASK(nir_dest_num_components(instr->dest)); ntt_emit_load_sysval() local
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/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir.c410 if (!(vec->dest.write_mask & (1 << i)) || vec->src[i].src.ssa != ssa) in vec_dest_has_swizzle()
455 .write_mask = inst_write_mask_compose(mask, reg_writemask[t]), in ra_dest()
473 /* compose alu write_mask with RA write mask */ in emit_alu()
475 dst.write_mask = inst_write_mask_compose(alu->dest.write_mask, dst.write_mask); in emit_alu()
565 .dst.write_mask = 0x1, in emit_intrinsic()
691 unsigned write_mask = (1u << start_idx); in insert_vec_mov() local
703 if (!(vec->dest.write_mask & (1 << i))) in insert_vec_mov()
709 write_mask | in insert_vec_mov()
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H A Detnaviv_compiler_nir.h104 unsigned swizzle = 0, write_mask = 0; in update_swiz_mask() local
107 if (!(alu->dest.write_mask & (1 << i))) in update_swiz_mask()
117 write_mask |= 1 << i; in update_swiz_mask()
120 *mask = write_mask; in update_swiz_mask()
/third_party/mesa3d/src/compiler/nir/tests/
H A Dserialize_tests.cpp172 fma_alu->dest.write_mask = (1 << GetParam()) - 1; in TEST_P()
202 fma_alu->dest.write_mask = 1 | (1 << (GetParam() - 1)); in TEST_P()
230 fma_alu->dest.write_mask = 1 | (1 << (GetParam() - 1)); in TEST_P()
259 fma_alu->dest.write_mask = 0x3; in TEST_P()
H A Dcomparison_pre_tests.cpp508 flt->dest.write_mask = 1; in TEST_F()
523 fadd->dest.write_mask = 1; in TEST_F()
565 flt->dest.write_mask = 1; in TEST_F()
580 fadd->dest.write_mask = 3; in TEST_F()
/third_party/mesa3d/src/microsoft/vulkan/
H A Ddzn_nir.c163 .write_mask = 0x1, .access = ACCESS_NON_READABLE, in dzn_nir_indirect_draw_shader()
271 .write_mask = mask, .access = ACCESS_NON_READABLE, .align_mul = 4); in dzn_nir_indirect_draw_shader()
283 .write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 16); in dzn_nir_indirect_draw_shader()
295 .write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 16); in dzn_nir_indirect_draw_shader()
298 .write_mask = 0xf, .access = ACCESS_NON_READABLE, .align_mul = 16); in dzn_nir_indirect_draw_shader()
456 .write_mask = 7, .access = ACCESS_NON_READABLE, .align_mul = 4); in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
464 .write_mask = 1, .access = ACCESS_NON_READABLE, .align_mul = 4); in dzn_nir_triangle_fan_prim_restart_rewrite_index_shader()
554 .write_mask = 7, .access = ACCESS_NON_READABLE, .align_mul = 4); in dzn_nir_triangle_fan_rewrite_index_shader()

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