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Searched refs:vcgt (Results 1 - 16 of 16) sorted by relevance

/third_party/ffmpeg/libavcodec/arm/
H A Dhevcdsp_deblock_neon.S108 vcgt.s16 q3, q0, q4
113 vcgt.s16 q5, q1, q5
130 vcgt.s16 q6, q1, q7
133 vcgt.s16 q6, q2, q7
240 vcgt.s16 q1, q1, q3
254 vcgt.s16 q1, q4, q1
267 vcgt.s16 q1, q4, q1
H A Dhevcdsp_sao_neon.S118 vcgt.u8 d8, d16, d17
122 vcgt.u8 d10, d16, d18
151 vcgt.u8 d8, d16, d17
155 vcgt.u8 d10, d16, d18
H A Dsbcdsp_neon.S410 vcgt.s32 q15, q15, q9
441 vcgt.s32 q15, q15, q9
468 vcgt.s32 q15, q15, q9
H A Dvp8dsp_neon.S307 vcgt.u8 q12, q12, q15 @ abs(P1-P0) > hev_thresh
309 vcgt.u8 q14, q13, q15 @ abs(Q1-Q0) > hev_thresh
/third_party/node/deps/v8/src/compiler/backend/arm/
H A Dcode-generator-arm.cc2269 __ vcgt(i.OutputSimd128Register(), i.InputSimd128Register(1), in AssembleArchInstruction()
2288 __ vcgt(dst, lhs, rhs); in AssembleArchInstruction()
2301 __ vcgt(dst, rhs, lhs); in AssembleArchInstruction()
2411 __ vcgt(NeonS32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2449 __ vcgt(NeonU32, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2601 __ vcgt(NeonS16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2648 __ vcgt(NeonU16, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2766 __ vcgt(NeonS8, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
2803 __ vcgt(NeonU8, i.OutputSimd128Register(), i.InputSimd128Register(0), in AssembleArchInstruction()
/third_party/vixl/test/aarch32/
H A Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc56 M(vcgt) \
212 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vcgt-a32.h"
H A Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc56 M(vcgt) \
212 #include "aarch32/traces/assembler-cond-dt-drt-drd-drn-drm-float-f32-only-vcgt-t32.h"
/third_party/node/deps/v8/src/diagnostics/arm/
H A Ddisasm-arm.cc2060 Format(instr, "vcgt.s'size3 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
2110 Format(instr, "vcgt.u'size3 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
2132 Format(instr, "vcgt.f32 'Qd, 'Qn, 'Qm"); in DecodeAdvancedSIMDDataProcessing()
/third_party/vixl/src/aarch32/
H A Dassembler-aarch32.h4094 void vcgt(Condition cond,
4099 void vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vcgt() function in vixl::aarch32::Assembler
4100 vcgt(al, dt, rd, rm, operand); in vcgt()
4103 void vcgt(Condition cond,
4108 void vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vcgt() function in vixl::aarch32::Assembler
4109 vcgt(al, dt, rd, rm, operand); in vcgt()
4112 void vcgt(
4114 void vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vcgt() function in vixl::aarch32::Assembler
4115 vcgt(al, dt, rd, rn, rm); in vcgt()
4118 void vcgt(
4120 void vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { vcgt() function in vixl::aarch32::Assembler
[all...]
H A Ddisasm-aarch32.h1608 void vcgt(Condition cond,
1614 void vcgt(Condition cond,
1620 void vcgt(
1623 void vcgt(
H A Ddisasm-aarch32.cc4169 void Disassembler::vcgt(Condition cond, in vcgt() function in vixl::aarch32::Disassembler
4183 void Disassembler::vcgt(Condition cond, in vcgt() function in vixl::aarch32::Disassembler
4197 void Disassembler::vcgt( in vcgt() function in vixl::aarch32::Disassembler
4208 void Disassembler::vcgt( in vcgt() function in vixl::aarch32::Disassembler
[all...]
H A Dassembler-aarch32.cc15377 void Assembler::vcgt(Condition cond, in vcgt() function in vixl::aarch32::Assembler
15414 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand); in vcgt()
15417 void Assembler::vcgt(Condition cond, in vcgt() function in vixl::aarch32::Assembler
15454 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rm, operand); in vcgt()
15457 void Assembler::vcgt( in vcgt() function in vixl::aarch32::Assembler
15501 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm); in vcgt()
15504 void Assembler::vcgt( in vcgt() function in vixl::aarch32::Assembler
15548 Delegate(kVcgt, &Assembler::vcgt, cond, dt, rd, rn, rm); in vcgt()
H A Dmacro-assembler-aarch32.h7250 vcgt(cond, dt, rd, rm, operand); in MacroAssembler()
7272 vcgt(cond, dt, rd, rm, operand); in MacroAssembler()
7291 vcgt(cond, dt, rd, rn, rm); in MacroAssembler()
7310 vcgt(cond, dt, rd, rn, rm); in MacroAssembler()
/third_party/node/deps/v8/src/wasm/baseline/arm/
H A Dliftoff-assembler-arm.h2801 vcgt(tmp, left, right); in emit_f32x4_pmin()
2820 vcgt(tmp, right, left); in emit_f32x4_pmax()
3698 vcgt(NeonS8, liftoff::GetSimd128Register(dst),
3704 vcgt(NeonU8, liftoff::GetSimd128Register(dst),
3735 vcgt(NeonS16, liftoff::GetSimd128Register(dst),
3741 vcgt(NeonU16, liftoff::GetSimd128Register(dst),
3772 vcgt(NeonS32, liftoff::GetSimd128Register(dst),
3778 vcgt(NeonU32, liftoff::GetSimd128Register(dst),
3833 vcgt(liftoff::GetSimd128Register(dst), liftoff::GetSimd128Register(rhs),
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.h964 void vcgt(QwNeonRegister dst, QwNeonRegister src1, QwNeonRegister src2);
965 void vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1,
H A Dassembler-arm.cc4918 void Assembler::vcgt(QwNeonRegister dst, QwNeonRegister src1, in vcgt() function in v8::internal::Assembler
4921 // Qd = vcgt(Qn, Qm) SIMD floating point compare greater than. in vcgt()
4926 void Assembler::vcgt(NeonDataType dt, QwNeonRegister dst, QwNeonRegister src1, in vcgt() function in v8::internal::Assembler
4929 // Qd = vcgt(Qn, Qm) SIMD integer compare greater than. in vcgt()

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