| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 200 {ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
201 {ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0}, in getCastInstrCost()
219 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
220 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
224 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
227 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
228 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
256 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
257 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
271 { ISD::FP_TO_SINT, MVT::v4i16, MV in getCastInstrCost()
[all...] |
| H A D | ARMISelLowering.cpp | 377 // It is legal to extload from v4i8 to v4i16 or v4i32. in addMVEVectorTypes()
379 addAllExtLoads(MVT::v4i32, MVT::v4i16, Legal); in addMVEVectorTypes()
382 // It is legal to sign extend from v4i8/v4i16 to v4i32 or v8i8 to v8i16. in addMVEVectorTypes()
384 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); in addMVEVectorTypes()
390 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Legal); in addMVEVectorTypes()
397 for (auto VT : {MVT::v8i8, MVT::v4i8, MVT::v4i16}) { in addMVEVectorTypes()
759 addDRTypeForNEON(MVT::v4i16); in ARMTargetLowering()
855 setOperationAction(ISD::SDIV, MVT::v4i16, Custom); in ARMTargetLowering()
857 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); in ARMTargetLowering()
863 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custo in ARMTargetLowering()
[all...] |
| H A D | ARMISelDAGToDAG.cpp | 1728 if (Align >= 2 && LoadedVT == MVT::v4i16 && in tryMVEIndexedLoad()
2033 case MVT::v4i16: OpcodeIndex = 1; break; in SelectVLD()
2175 case MVT::v4i16: OpcodeIndex = 1; break; in SelectVST()
2342 case MVT::v4i16: OpcodeIndex = 1; break; in SelectVLDSTLane()
2724 case MVT::v4i16: in SelectVLDDup()
3666 case MVT::v4i16: Opc = ARM::VZIPd16; break; in Select()
3689 case MVT::v4i16: Opc = ARM::VUZPd16; break; in Select()
3712 case MVT::v4i16: Opc = ARM::VTRNd16; break; in Select()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelDAGToDAG.cpp | 604 case MVT::v4i16: in tryMLAV64LaneV128()
1851 // Example: v8i16 -> v4i16 means the extract must begin at index 4. in tryHighFPExt()
3188 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3215 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3242 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3269 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3296 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3323 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3350 } else if (VT == MVT::v4i16 || VT == MVT::v4f16) { in Select()
3377 } else if (VT == MVT::v4i16 || V in Select()
[all...] |
| H A D | AArch64TargetTransformInfo.cpp | 302 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i32, 1 }, in getCastInstrCost()
308 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
309 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
343 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
345 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 }, in getCastInstrCost()
382 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~2 in getCastInstrCost()
383 { ISD::FP_TO_SINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
385 { ISD::FP_TO_UINT, MVT::v4i16, MVT::v4f32, 2 }, in getCastInstrCost()
945 {ISD::ADD, MVT::v4i16, 1}, in getArithmeticReductionCost() member in MVT
964 { TTI::SK_Broadcast, MVT::v4i16, in getShuffleCost()
[all...] |
| H A D | AArch64ISelLowering.cpp | 151 addDRTypeForNEON(MVT::v4i16); in AArch64TargetLowering()
757 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in AArch64TargetLowering()
758 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in AArch64TargetLowering()
764 setOperationPromotedToType(ISD::UINT_TO_FP, MVT::v4i16, MVT::v4i32); in AArch64TargetLowering()
765 setOperationPromotedToType(ISD::SINT_TO_FP, MVT::v4i16, MVT::v4i32); in AArch64TargetLowering()
780 for (MVT VT : { MVT::v8i8, MVT::v4i16, MVT::v2i32, in AArch64TargetLowering()
850 setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom); in AArch64TargetLowering()
1159 } else if (VT == MVT::v4i16 || VT == MVT::v8i16) { in computeKnownBitsForTargetNode()
2750 return MVT::v4i16; in getExtensionTo64Bits()
3068 // Custom lower trunc store for v4i8 vectors, since it is promoted to v4i16
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/Support/ |
| H A D | MachineValueType.h | 85 v4i16 = 37, // 4 x i16
343 SimpleTy == MVT::v4i16 || SimpleTy == MVT::v2i32 || in is64BitVector()
463 case v4i16: in getVectorElementType()
618 case v4i16: in getVectorNumElements()
739 case v4i16: in getSizeInBits()
950 if (NumElements == 4) return MVT::v4i16; in getVectorVT()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86TargetTransformInfo.cpp | 1376 { ISD::UINT_TO_FP, MVT::v4f64, MVT::v4i16, 2 }, in getCastInstrCost()
1421 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, in getCastInstrCost()
1422 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 1 }, in getCastInstrCost()
1429 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 2 }, in getCastInstrCost()
1452 { ISD::SIGN_EXTEND, MVT::v4i64, MVT::v4i16, 4 }, in getCastInstrCost()
1453 { ISD::ZERO_EXTEND, MVT::v4i64, MVT::v4i16, 3 }, in getCastInstrCost()
1463 { ISD::TRUNCATE, MVT::v4i16, MVT::v4i64, 4 }, in getCastInstrCost()
1476 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 3 }, in getCastInstrCost()
1477 { ISD::SINT_TO_FP, MVT::v4f64, MVT::v4i16, 3 }, in getCastInstrCost()
1489 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, in getCastInstrCost()
[all...] |
| H A D | X86ISelLowering.cpp | 877 MVT::v2i16, MVT::v4i16, MVT::v2i32 }) { in X86TargetLowering()
972 for (auto VT : {MVT::v2i8, MVT::v4i8, MVT::v8i8, MVT::v2i16, MVT::v4i16}) { in X86TargetLowering()
1005 setOperationAction(ISD::LOAD, MVT::v4i16, Custom); in X86TargetLowering()
1008 setOperationAction(ISD::STORE, MVT::v4i16, Custom); in X86TargetLowering()
1012 setOperationAction(ISD::BITCAST, MVT::v4i16, Custom); in X86TargetLowering()
1027 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom); in X86TargetLowering()
1111 setLoadExtAction(LoadExtOp, MVT::v4i32, MVT::v4i16, Legal); in X86TargetLowering()
1323 setLoadExtAction(LoadExtOp, MVT::v4i64, MVT::v4i16, Legal); in X86TargetLowering()
1866 setTruncStoreAction(MVT::v4i64, MVT::v4i16, Legal); in X86TargetLowering()
1875 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Lega in X86TargetLowering()
[all...] |
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIISelLowering.cpp | 157 addRegisterClass(MVT::v4i16, &AMDGPU::SReg_64RegClass); in SITargetLowering()
196 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Expand); in SITargetLowering()
234 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom); in SITargetLowering()
262 MVT::v2i64, MVT::v2f64, MVT::v4i16, MVT::v4f16, in SITargetLowering()
313 setOperationAction(ISD::BUILD_VECTOR, MVT::v4i16, Custom); in SITargetLowering()
319 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); in SITargetLowering()
332 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i16, Custom); in SITargetLowering()
334 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i16, Custom); in SITargetLowering()
525 for (MVT VT : {MVT::v2i16, MVT::v2f16, MVT::v4i16, MVT::v4f16}) { in SITargetLowering()
572 setOperationAction(ISD::LOAD, MVT::v4i16, Promot in SITargetLowering()
[all...] |
| H A D | R600ISelLowering.cpp | 111 setTruncStoreAction(MVT::v4i32, MVT::v4i16, Custom); in R600TargetLowering()
199 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Expand); in R600TargetLowering()
|
| H A D | AMDGPUISelLowering.cpp | 147 setLoadExtAction(ISD::EXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
148 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand); in AMDGPUTargetLowering()
1228 if (VT == MVT::v4i16 || VT == MVT::v4f16) { in LowerCONCAT_VECTORS()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 611 VT == MVT::v4i16 || VT == MVT::v8i8 || in getPostIndexedAddressParts()
1328 addRegisterClass(MVT::v4i16, &Hexagon::DoubleRegsRegClass); in HexagonTargetLowering()
1526 setLoadExtAction(ISD::EXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1527 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1528 setLoadExtAction(ISD::SEXTLOAD, MVT::v4i16, MVT::v4i8, Legal); in HexagonTargetLowering()
1536 MVT::v8i8, MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1557 MVT::v2i16, MVT::v4i16, MVT::v2i32}) { in HexagonTargetLowering()
1562 for (MVT VT : {MVT::v2i16, MVT::v4i8, MVT::v8i8, MVT::v2i32, MVT::v4i16, in HexagonTargetLowering()
1579 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4i16, Custom); in HexagonTargetLowering()
1607 MVT::v2i16, MVT::v2i32, MVT::v4i8, MVT::v4i16, MV in HexagonTargetLowering()
[all...] |
| H A D | HexagonISelDAGToDAG.cpp | 104 case MVT::v4i16: in SelectIndexedLoad()
494 case MVT::v4i16: in SelectIndexedStore()
|
| H A D | HexagonInstrInfo.cpp | 2656 case MVT::v4i16: in isValidAutoIncImm()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | ValueTypes.cpp | 182 case MVT::v4i16: return VectorType::get(Type::getInt16Ty(Context), 4); in getTypeForEVT()
|
| /third_party/mesa3d/src/amd/llvm/ |
| H A D | ac_llvm_build.h | 85 LLVMTypeRef v4i16; member
|
| H A D | ac_nir_to_llvm.c | 1205 result = LLVMBuildBitCast(ctx->ac.builder, src[0], ctx->ac.v4i16, ""); in visit_alu()
|
| H A D | ac_llvm_build.c | 90 ctx->v4i16 = LLVMVectorType(ctx->i16, 4); in ac_llvm_context_init()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyISelLowering.cpp | 265 setLoadExtAction(Ext, MVT::v4i32, MVT::v4i16, Legal); in WebAssemblyTargetLowering()
573 (ExtT == MVT::v4i32 && MemT == MVT::v4i16) || in isVectorLoadExtDesirable()
|
| /third_party/vk-gl-cts/external/vulkancts/modules/vulkan/ray_tracing/ |
| H A D | vktRayTracingDataSpillTests.cpp | 1397 using v4i16 = tcu::Vector<deInt16, 4>;
1545 else if (dataType == DataType::INT16) GEN_V4_FILL(v4i16); in fillInputBuffer()
|
| /third_party/vk-gl-cts/external/vulkancts/modules_no_buildgn/vulkan/ray_tracing/ |
| H A D | vktRayTracingDataSpillTests.cpp | 1397 using v4i16 = tcu::Vector<deInt16, 4>;
1545 else if (dataType == DataType::INT16) GEN_V4_FILL(v4i16); in fillInputBuffer()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelLowering.cpp | 143 case MVT::v4i16: in IsPTXVectorType()
2311 case MVT::v4i16: in LowerSTOREVector()
4802 case MVT::v4i16: in ReplaceLoadVector()
|
| /third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCISelLowering.cpp | 699 setOperationAction(ISD::TRUNCATE, MVT::v4i16, Custom); in PPCTargetLowering()
874 setOperationAction(ISD::UINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
878 setOperationAction(ISD::SINT_TO_FP, MVT::v4i16, Custom); in PPCTargetLowering()
960 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Legal); in PPCTargetLowering()
13275 // input types (i.e. it can't handle things like v4i16) so do not run before in DAGCombineBuildVector()
|