Searched refs:v3b (Results 1 - 4 of 4) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/tests/ |
| H A D | test_to_hw_instr.cpp | 167 //~gfx[67]! v3b: %0:v[0][0:24] = v_alignbyte_b32 %0:v[2][0:8], %0:v[0][16:32], 2
170 Definition(v0_lo, v3b), Operand(v1_lo, v1b),
178 //~gfx[67]! v3b: %0:v[0][0:24] = v_alignbyte_b32 %0:v[2][0:8], %0:v[0][16:32], 2
179 //~gfx[67]! v3b: %0:v[0][8:32] = v_lshlrev_b32 8, %0:v[0][0:24]
191 //~gfx[67]! v3b: %0:v[0][0:24] = v_cvt_pk_u16_u32 %0:v[0][0:16], %0:v[0][0:8]
192 //~gfx[67]! v3b: %0:v[0][0:24] = v_and_b32 0xffffff, %0:v[0][0:24]
346 Definition(v0_lo, v3b), Definition(v1_lo, v3b),
347 Operand(v1_lo, v3b), Operand(v0_lo, v3b));
[all...] |
| H A D | test_regalloc.cpp | 158 //>> v3b: %0:v[0][0:24] = v_and_b32 0xffffff, %0:v[0][0:24]
161 bld.pseudo(aco_opcode::p_create_vector, bld.def(v1), Operand(v3b), Operand(tmp));
177 //! v3b: %0:v[1][0:24] = v_and_b32 0xffffff, %0:v[1][0:24]
180 bld.pseudo(aco_opcode::p_create_vector, bld.def(v2), inputs[1], Operand(v3b), Operand(tmp));
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| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_ir.h | 329 v3b = v3 | (1 << 7), member
396 static constexpr RegClass v3b{RegClass::v3b};
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| H A D | aco_instruction_selection.cpp | 8666 bld.def(src.regClass() == v1b ? v3b : v2b), tmp);
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