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Searched refs:v1b (Results 1 - 6 of 6) sorted by relevance

/third_party/mesa3d/src/amd/compiler/tests/
H A Dtest_to_hw_instr.cpp150 Definition(v0_lo, v1b), Definition(v1_lo, v1b),
151 Operand(v1_lo, v1b), Operand(v0_lo, v1b));
154 //~gfx[67]! v1b: %0:v[1][24:32] = v_lshlrev_b32 24, %0:v[1][0:8]
160 Operand(v1_lo, v1b), Operand(v0_lo, v1b));
163 //~gfx[67]! v1b: %0:v[1][24:32] = v_lshlrev_b32 24, %0:v[1][0:8]
170 Definition(v0_lo, v3b), Operand(v1_lo, v1b),
171 Operand(v0_lo, v1b), Operan
[all...]
H A Dtest_regalloc.cpp156 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::zero());
174 Temp tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), inputs[0], Operand::c32(4u));
H A Dtest_sdwa.cpp40 sdwa = &bld.vop2_sdwa(aco_opcode::v_mul_f32, bld.def(v1b), inputs[0], inputs[1]).instr->sdwa();
/third_party/mesa3d/src/amd/compiler/
H A Daco_lower_to_hw_instr.cpp513 if (src.regClass() == v1b) { in emit_reduction()
1086 assert(dst.regClass() == v1b || dst.regClass() == v2b); in copy_constant()
1093 if (dst.regClass() == v1b && use_sdwa) { in copy_constant()
1274 } else if (def.regClass() == v1b && ctx->program->gfx_level >= GFX11) { in do_copy()
1321 swap_subdword_gfx11(bld, def, Operand(def_other_half.advance(op.physReg().byte() & 1), v1b)); in swap_subdword_gfx11()
1350 tmp.op = Operand(op, v1b); in do_swap()
1351 tmp.def = Definition(def, v1b); in do_swap()
2237 assert(dst.regClass() == v2b || dst.regClass() == v1b || op.regClass() == v2b || in lower_to_hw_instr()
2238 op.regClass() == v1b); in lower_to_hw_instr()
H A Daco_ir.h327 v1b = v1 | (1 << 7), member
394 static constexpr RegClass v1b{RegClass::v1b};
H A Daco_instruction_selection.cpp1492 if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
1645 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
1661 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
1677 } else if (dst.regClass() == v1 || dst.regClass() == v2b || dst.regClass() == v1b) {
2835 tmp = bld.pseudo(aco_opcode::p_extract_vector, bld.def(v1b), tmp, Operand::zero());
8661 if (src.regClass() == v1b || src.regClass() == v2b) {
8666 bld.def(src.regClass() == v1b ? v3b : v2b), tmp);
8709 if (src.regClass() == v1b || src.regClass() == v2b || src.regClass() == v1) {
8945 } else if (dst.regClass() == v1b) {

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