| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | hevcdsp_sao_neon.S | 102 uzp2 v1.16b, v3.16b, v3.16b // sao_offset_val -> upper
159 uzp2 v1.16b, v3.16b, v3.16b
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| /third_party/vixl/src/aarch64/ |
| H A D | logic-aarch64.cc | 641 uzp2(vform, temp2, src1, src2); in addp()
2730 uzp2(vform, src1_i, src1, zero);
2732 uzp2(vform, src2_i, src2, zero);
2772 uzp2(vform, src2_b, src2, zero);
2774 uzp2(vform, src1_a, src1, zero);
2775 uzp2(vform, src2_a, src2, zero);
2780 uzp2(vform, srca_i, srca, zero);
4084 uzp2(vform, src2_b, src2, zero);
4086 uzp2(vform, src1_a, src1, zero);
4087 uzp2(vfor
[all...] |
| H A D | assembler-aarch64.h | 3210 void uzp2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
5860 void uzp2(const PRegisterWithLaneSize& pd,
5865 void uzp2(const ZRegister& zd, const ZRegister& zn, const ZRegister& zm);
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| H A D | simulator-aarch64.cc | 3257 uzp2(vform_half, zn_t, zn, zero); in Simulator()
3258 uzp2(vform_half, zm_t, zm, zero); in Simulator()
9622 uzp2(vf, rd, rn, rm); in Simulator()
13247 uzp2(vform, temp0, temp0, temp1); in Simulator()
13315 uzp2(vform, zd, zn, zm); in Simulator()
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| H A D | macro-assembler-aarch64.h | 2982 V(uzp2, Uzp2) \
6490 uzp2(pd, pn, pm); in Uzp2()
6495 uzp2(zd, zn, zm); in Uzp2()
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| H A D | simulator-aarch64.h | 4124 LogicVRegister uzp2(VectorFormat vform,
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| H A D | assembler-sve-aarch64.cc | 5522 void Assembler::uzp2(const PRegisterWithLaneSize& pd, in uzp2() function in vixl::aarch64::Assembler
5636 void Assembler::uzp2(const ZRegister& zd, in uzp2() function in vixl::aarch64::Assembler
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| H A D | assembler-aarch64.cc | 5439 void Assembler::uzp2(const VRegister& vd,
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2494 __ uzp2(v8.V16B(), v18.V16B(), v26.V16B()); in GenerateTestSequenceNEON()
2495 __ uzp2(v21.V2D(), v22.V2D(), v24.V2D()); in GenerateTestSequenceNEON()
2496 __ uzp2(v20.V2S(), v21.V2S(), v2.V2S()); in GenerateTestSequenceNEON()
2497 __ uzp2(v16.V4H(), v31.V4H(), v6.V4H()); in GenerateTestSequenceNEON()
2498 __ uzp2(v25.V4S(), v11.V4S(), v8.V4S()); in GenerateTestSequenceNEON()
2499 __ uzp2(v31.V8B(), v31.V8B(), v13.V8B()); in GenerateTestSequenceNEON()
2500 __ uzp2(v8.V8H(), v17.V8H(), v1.V8H()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2757 TEST_NEON(uzp2_0, uzp2(v0.V8B(), v1.V8B(), v2.V8B()))
2758 TEST_NEON(uzp2_1, uzp2(v0.V16B(), v1.V16B(), v2.V16B()))
2759 TEST_NEON(uzp2_2, uzp2(v0.V4H(), v1.V4H(), v2.V4H()))
2760 TEST_NEON(uzp2_3, uzp2(v0.V8H(), v1.V8H(), v2.V8H()))
2761 TEST_NEON(uzp2_4, uzp2(v0.V2S(), v1.V2S(), v2.V2S()))
2762 TEST_NEON(uzp2_5, uzp2(v0.V4S(), v1.V4S(), v2.V4S()))
2763 TEST_NEON(uzp2_6, uzp2(v0.V2D(), v1.V2D(), v2.V2D()))
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| H A D | test-disasm-sve-aarch64.cc | 5472 COMPARE(uzp2(p6.VnB(), p11.VnB(), p2.VnB()), "uzp2 p6.b, p11.b, p2.b"); in TEST()
5473 COMPARE(uzp2(p6.VnH(), p11.VnH(), p2.VnH()), "uzp2 p6.h, p11.h, p2.h"); in TEST()
5474 COMPARE(uzp2(p6.VnS(), p11.VnS(), p2.VnS()), "uzp2 p6.s, p11.s, p2.s"); in TEST()
5475 COMPARE(uzp2(p6.VnD(), p11.VnD(), p2.VnD()), "uzp2 p6.d, p11.d, p2.d"); in TEST()
5520 COMPARE(uzp2(z22.VnB(), z26.VnB(), z15.VnB()), "uzp2 z2 in TEST()
[all...] |
| H A D | test-simulator-aarch64.cc | 4965 DEFINE_TEST_NEON_3SAME(uzp2, Basic)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 678 uzp2(vform, temp2, src1, src2); in addp()
2903 LogicVRegister Simulator::uzp2(VectorFormat vform, LogicVRegister dst, in uzp2() function in v8::internal::Simulator
3612 uzp2(vform, temp2, src1, src2); \
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| H A D | simulator-arm64.h | 1887 LogicVRegister uzp2(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 6033 uzp2(vf, rd, rn, rm);
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1339 void uzp2(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 480 V(uzp2, Uzp2) \
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| H A D | assembler-arm64.cc | 1556 void Assembler::uzp2(const VRegister& vd, const VRegister& vn, in uzp2() function in v8::internal::Assembler
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