| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2461 __ usra(d28, d27, 37); in GenerateTestSequenceNEON()
2462 __ usra(v5.V16B(), v22.V16B(), 5); in GenerateTestSequenceNEON()
2463 __ usra(v2.V2D(), v19.V2D(), 33); in GenerateTestSequenceNEON()
2464 __ usra(v0.V2S(), v0.V2S(), 21); in GenerateTestSequenceNEON()
2465 __ usra(v7.V4H(), v6.V4H(), 12); in GenerateTestSequenceNEON()
2466 __ usra(v4.V4S(), v17.V4S(), 9); in GenerateTestSequenceNEON()
2467 __ usra(v9.V8B(), v12.V8B(), 7); in GenerateTestSequenceNEON()
2468 __ usra(v3.V8H(), v27.V8H(), 14); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2724 TEST_NEON(usra_0, usra(v0.V8B(), v1.V8B(), 6))
2725 TEST_NEON(usra_1, usra(v0.V16B(), v1.V16B(), 4))
2726 TEST_NEON(usra_2, usra(v0.V4H(), v1.V4H(), 9))
2727 TEST_NEON(usra_3, usra(v0.V8H(), v1.V8H(), 3))
2728 TEST_NEON(usra_4, usra(v0.V2S(), v1.V2S(), 12))
2729 TEST_NEON(usra_5, usra(v0.V4S(), v1.V4S(), 14))
2730 TEST_NEON(usra_6, usra(v0.V2D(), v1.V2D(), 27))
2731 TEST_NEON(usra_7, usra(d0, d1, 54))
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| H A D | test-disasm-sve-aarch64.cc | 6420 COMPARE(usra(z0.VnB(), z8.VnB(), 1), "usra z0.b, z8.b, #1"); in TEST()
6421 COMPARE(usra(z0.VnB(), z8.VnB(), 2), "usra z0.b, z8.b, #2"); in TEST()
6422 COMPARE(usra(z0.VnB(), z8.VnB(), 5), "usra z0.b, z8.b, #5"); in TEST()
6423 COMPARE(usra(z0.VnB(), z8.VnB(), 8), "usra z0.b, z8.b, #8"); in TEST()
6424 COMPARE(usra(z0.VnH(), z8.VnH(), 1), "usra z in TEST()
[all...] |
| H A D | test-simulator-aarch64.cc | 2470 // test for shift and accumulate instructions (srsra/ssra/usra/ursra). in Test2OpImmNEON_Helper()
4789 DEFINE_TEST_NEON_2OPIMM(usra, Basic, TypeWidth)
4821 DEFINE_TEST_NEON_2OPIMM_SCALAR_D(usra, Basic, TypeWidth)
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| H A D | test-api-movprfx-aarch64.cc | 2397 __ usra(z0.VnB(), z8.VnB(), 1); in TEST()
3138 __ usra(z0.VnB(), z8.VnB(), 1); in TEST()
3572 __ usra(z0.VnB(), z0.VnB(), 1); in TEST()
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1363 void usra(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1250 V(usra, Usra)
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| H A D | assembler-arm64.cc | 1724 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) { in usra() function in v8::internal::Assembler
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 2250 ShiftRightAccumulate(&Assembler::usra, zd, za, zn, shift); in Usra()
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| H A D | logic-aarch64.cc | 1773 LogicVRegister Simulator::usra(VectorFormat vform,
3958 usra(vform, temp_hi, temp_lo, esize - 1);
3964 usra(vform, temp_hi, temp_lo, esize - 1);
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| H A D | assembler-aarch64.h | 3234 void usra(const VRegister& vd, const VRegister& vn, int shift);
6853 void usra(const ZRegister& zda, const ZRegister& zn, int shift);
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| H A D | simulator-aarch64.cc | 3238 usra(vform, zd, zn, shift_dist); in Simulator()
9354 usra(vf, rd, rn, right_shift); in Simulator()
9457 usra(vf, rd, rn, right_shift); in Simulator()
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| H A D | simulator-aarch64.h | 4200 LogicVRegister usra(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 5668 void Assembler::usra(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | assembler-sve-aarch64.cc | 9635 void Assembler::usra(const ZRegister& zda, const ZRegister& zn, int shift) { in usra() function in vixl::aarch64::Assembler
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| H A D | macro-assembler-aarch64.h | 3189 V(usra, Usra)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1919 LogicVRegister usra(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5771 usra(vf, rd, rn, right_shift);
5870 usra(vf, rd, rn, right_shift);
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| H A D | simulator-logic-arm64.cc | 1479 LogicVRegister Simulator::usra(VectorFormat vform, LogicVRegister dst, in usra() function in v8::internal::Simulator
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