| /third_party/ffmpeg/libswscale/aarch64/ |
| H A D | output.S | 29 ushll2 v2.4S, v0.8H, #12 // extend dither to 32-bit with left shift by 12 (part 2)
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| H A D | yuv2rgb_neon.S | 166 ushll2 v27.8H, v2.16B, #3 // Y2*(1<<3)
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | h264dsp_neon.S | 214 ushll2 v21.8h, v6.16b, #1
215 ushll2 v23.8h, v1.16b, #1
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| H A D | vc1dsp_neon.S | 1059 ushll2 v3.8h, v3.16b, #1 // 2*P1[8..15]
1061 ushll2 v19.8h, v1.16b, #1 // 2*P5[8..15]
1074 ushll2 v6.8h, v6.16b, #1 // 2*P3[8..15]
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| H A D | vp9lpf_neon.S | 148 ushll2 \dst2, \in\().16b, \shift
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1958 void ushll2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1248 V(ushll2, Ushll2) \
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| H A D | assembler-arm64.cc | 1681 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) { in ushll2() function in v8::internal::Assembler
1691 ushll2(vd, vn, 0); in uxtl2()
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2439 __ ushll2(v8.V2D(), v29.V4S(), 7); in GenerateTestSequenceNEON()
2440 __ ushll2(v29.V4S(), v9.V8H(), 2); in GenerateTestSequenceNEON()
2441 __ ushll2(v5.V8H(), v24.V16B(), 6); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2694 TEST_NEON(ushll2_0, ushll2(v0.V8H(), v1.V16B(), 7))
2695 TEST_NEON(ushll2_1, ushll2(v0.V4S(), v1.V8H(), 15))
2696 TEST_NEON(ushll2_2, ushll2(v0.V2D(), v1.V4S(), 14))
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1907 LogicVRegister ushll2(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5907 ushll2(vf, rd, rn, left_shift);
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| H A D | simulator-logic-arm64.cc | 1386 LogicVRegister Simulator::ushll2(VectorFormat vform, LogicVRegister dst, in ushll2() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 4176 LogicVRegister ushll2(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 5607 void Assembler::ushll2(const VRegister& vd, const VRegister& vn, int shift) {
5622 ushll2(vd, vn, 0);
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| H A D | assembler-aarch64.h | 3016 void ushll2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | logic-aarch64.cc | 1564 LogicVRegister Simulator::ushll2(VectorFormat vform, in ushll2() function in vixl::aarch64::Simulator
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| H A D | macro-assembler-aarch64.h | 3204 V(shll2, ushll2, Ushll2)
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| H A D | simulator-aarch64.cc | 9494 ushll2(vf, rd, rn, left_shift); in Simulator()
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