| /third_party/ltp/tools/sparse/sparse-src/validation/backend/ |
| H A D | bitwise-ops.c | 6 static unsigned int ushl(unsigned int x, unsigned int y) in ushl() function
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.cc | 4359 ushl(vf, rd, rn, rm);
4392 ushl(vf, rd, rn, rm).UnsignedSaturate(vf);
4398 ushl(vf, rd, rn, rm).Round(vf);
4404 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf);
5565 ushl(vf, rd, rn, rm);
5589 ushl(vf, rd, rn, rm).UnsignedSaturate(vf);
5595 ushl(vf, rd, rn, rm).Round(vf);
5601 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf);
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| H A D | simulator-logic-arm64.cc | 1344 return ushl(vform, dst, src, shiftreg); in shl()
1383 return ushl(vform, dst, extendedreg, shiftreg); in ushll()
1392 return ushl(vform, dst, extendedreg, shiftreg); in ushll2()
1422 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform); in uqshl()
1461 return ushl(vform, dst, src, shiftreg); in ushr()
1603 LogicVRegister Simulator::ushl(VectorFormat vform, LogicVRegister dst, in ushl() function in v8::internal::Simulator
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| H A D | simulator-arm64.h | 1757 LogicVRegister ushl(VectorFormat vform, LogicVRegister dst,
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 7529 ushl(vf, rd, rn, rm); in Simulator()
7562 ushl(vf, rd, rn, rm).UnsignedSaturate(vf); in Simulator()
7568 ushl(vf, rd, rn, rm).Round(vf); in Simulator()
7574 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf); in Simulator()
9048 ushl(vf, rd, rn, rm); in Simulator()
9072 ushl(vf, rd, rn, rm).UnsignedSaturate(vf); in Simulator()
9078 ushl(vf, rd, rn, rm).Round(vf); in Simulator()
9084 ushl(vf, rd, rn, rm).Round(vf).UnsignedSaturate(vf); in Simulator()
9837 ushl(vform, result, zdn, zm, shift_in_ls_byte) in Simulator()
9842 ushl(vfor in Simulator()
[all...] |
| H A D | logic-aarch64.cc | 1508 return ushl(vform, dst, src, shiftreg); in shl()
1560 return ushl(vform, dst, extendedreg, shiftreg); in ushll()
1572 return ushl(vform, dst, extendedreg, shiftreg); in ushll2()
1700 return ushl(vform, dst, src, shiftreg).UnsignedSaturate(vform);
1748 return ushl(vform, dst, src, shiftreg);
1957 LogicVRegister Simulator::ushl(VectorFormat vform,
2018 ushl(vform, dst, src1, temp, false);
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| H A D | simulator-aarch64.h | 3836 LogicVRegister ushl(VectorFormat vform,
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| H A D | assembler-aarch64.h | 2713 void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | assembler-aarch64.cc | 4172 V(ushl, NEON_USHL, vd.IsVector() || vd.Is1D()) \
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| H A D | macro-assembler-aarch64.h | 2976 V(ushl, Ushl) \
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2428 __ ushl(d31, d0, d16); in GenerateTestSequenceNEON()
2429 __ ushl(v0.V16B(), v6.V16B(), v2.V16B()); in GenerateTestSequenceNEON()
2430 __ ushl(v18.V2D(), v1.V2D(), v18.V2D()); in GenerateTestSequenceNEON()
2431 __ ushl(v27.V2S(), v7.V2S(), v29.V2S()); in GenerateTestSequenceNEON()
2432 __ ushl(v14.V4H(), v14.V4H(), v13.V4H()); in GenerateTestSequenceNEON()
2433 __ ushl(v22.V4S(), v4.V4S(), v9.V4S()); in GenerateTestSequenceNEON()
2434 __ ushl(v23.V8B(), v22.V8B(), v27.V8B()); in GenerateTestSequenceNEON()
2435 __ ushl(v21.V8H(), v25.V8H(), v8.V8H()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2697 TEST_NEON(ushl_0, ushl(v0.V8B(), v1.V8B(), v2.V8B()))
2698 TEST_NEON(ushl_1, ushl(v0.V16B(), v1.V16B(), v2.V16B()))
2699 TEST_NEON(ushl_2, ushl(v0.V4H(), v1.V4H(), v2.V4H()))
2700 TEST_NEON(ushl_3, ushl(v0.V8H(), v1.V8H(), v2.V8H()))
2701 TEST_NEON(ushl_4, ushl(v0.V2S(), v1.V2S(), v2.V2S()))
2702 TEST_NEON(ushl_5, ushl(v0.V4S(), v1.V4S(), v2.V4S()))
2703 TEST_NEON(ushl_6, ushl(v0.V2D(), v1.V2D(), v2.V2D()))
2704 TEST_NEON(ushl_7, ushl(d0, d1, d2))
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| H A D | test-simulator-aarch64.cc | 4644 DEFINE_TEST_NEON_3SAME(ushl, Basic)
4701 DEFINE_TEST_NEON_3SAME_SCALAR_D(ushl, Basic)
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1102 void ushl(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 474 V(ushl, Ushl) \
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| H A D | assembler-arm64.cc | 3068 V(ushl, NEON_USHL, vd.IsVector() || vd.Is1D()) \
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