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Searched refs:ucvtf (Results 1 - 20 of 20) sorted by relevance

/third_party/vixl/test/aarch64/
H A Dtest-disasm-fp-aarch64.cc321 COMPARE(ucvtf(d28, w29), "ucvtf d28, w29"); in TEST()
322 COMPARE(ucvtf(s28, w29), "ucvtf s28, w29"); in TEST()
323 COMPARE(ucvtf(d0, x1), "ucvtf d0, x1"); in TEST()
324 COMPARE(ucvtf(s0, x1), "ucvtf s0, x1"); in TEST()
325 COMPARE(ucvtf(d0, x1, 0), "ucvtf d in TEST()
[all...]
H A Dtest-cpu-features-aarch64.cc715 TEST_FP(ucvtf_0, ucvtf(d0, w1, 5))
716 TEST_FP(ucvtf_1, ucvtf(d0, x1, 5))
717 TEST_FP(ucvtf_2, ucvtf(s0, w1, 5))
718 TEST_FP(ucvtf_3, ucvtf(s0, x1, 5))
719 TEST_FP(ucvtf_4, ucvtf(d0, w1))
720 TEST_FP(ucvtf_5, ucvtf(d0, x1))
721 TEST_FP(ucvtf_6, ucvtf(s0, w1))
722 TEST_FP(ucvtf_7, ucvtf(s0, x1))
3379 TEST_FP_NEON(ucvtf_0, ucvtf(v0.V2S(), v1.V2S(), 5))
3380 TEST_FP_NEON(ucvtf_1, ucvtf(v
[all...]
H A Dtest-trace-aarch64.cc604 __ ucvtf(d0, d9); in GenerateTestSequenceFP()
605 __ ucvtf(d5, d22, 47); in GenerateTestSequenceFP()
606 __ ucvtf(d30, w27); in GenerateTestSequenceFP()
607 __ ucvtf(d3, w19, 1); in GenerateTestSequenceFP()
608 __ ucvtf(d28, x21); in GenerateTestSequenceFP()
609 __ ucvtf(d27, x30, 35); in GenerateTestSequenceFP()
610 __ ucvtf(s11, s5); in GenerateTestSequenceFP()
611 __ ucvtf(s0, s23, 14); in GenerateTestSequenceFP()
612 __ ucvtf(s20, w19); in GenerateTestSequenceFP()
613 __ ucvtf(s2 in GenerateTestSequenceFP()
[all...]
H A Dtest-api-movprfx-aarch64.cc586 __ ucvtf(z13.VnD(), p4.Merging(), z13.VnS()); in TEST()
589 __ ucvtf(z6.VnH(), p0.Merging(), z6.VnH()); in TEST()
592 __ ucvtf(z19.VnH(), p4.Merging(), z19.VnS()); in TEST()
595 __ ucvtf(z0.VnH(), p5.Merging(), z0.VnD()); in TEST()
1067 __ ucvtf(z8.VnD(), p3.Merging(), z1.VnS()); in TEST()
1070 __ ucvtf(z0.VnH(), p0.Merging(), z12.VnH()); in TEST()
1073 __ ucvtf(z8.VnH(), p3.Merging(), z4.VnS()); in TEST()
1076 __ ucvtf(z20.VnH(), p2.Merging(), z11.VnD()); in TEST()
1936 __ ucvtf(z7.VnD(), p3.Merging(), z26.VnS()); in TEST()
1939 __ ucvtf(z1 in TEST()
[all...]
H A Dtest-simulator-aarch64.cc4801 DEFINE_TEST_NEON_2OPIMM_HSD(ucvtf,
4832 DEFINE_TEST_NEON_2OPIMM_SCALAR_HSD(ucvtf,
H A Dtest-disasm-sve-aarch64.cc1860 COMPARE(ucvtf(z27.VnH(), p4.Merging(), z25.VnH()), in TEST()
1861 "ucvtf z27.h, p4/m, z25.h"); in TEST()
1862 COMPARE(ucvtf(z3.VnD(), p4.Merging(), z3.VnS()), "ucvtf z3.d, p4/m, z3.s"); in TEST()
1863 COMPARE(ucvtf(z24.VnH(), p2.Merging(), z29.VnS()), in TEST()
1864 "ucvtf z24.h, p2/m, z29.s"); in TEST()
1865 COMPARE(ucvtf(z29.VnS(), p5.Merging(), z14.VnS()), in TEST()
1866 "ucvtf z29.s, p5/m, z14.s"); in TEST()
1867 COMPARE(ucvtf(z7.VnD(), p2.Merging(), z14.VnD()), "ucvtf z in TEST()
[all...]
/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h1793 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0);
1799 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
H A Dmacro-assembler-arm64-inl.h994 ucvtf(fd, rn, fbits); in Ucvtf()
H A Dmacro-assembler-arm64.h1141 ucvtf(vd, vn, fbits); in Ucvtf()
H A Dassembler-arm64.cc2826 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) { in ucvtf() function in v8::internal::Assembler
2846 void Assembler::ucvtf(const VRegister& fd, const Register& rn, int fbits) { in ucvtf() function in v8::internal::Assembler
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc4109 ucvtf(fpf, rd, rn, 0, fpcr_rounding);
5419 ucvtf(fpf, rd, rn, 0, fpcr_rounding);
5807 ucvtf(vf, rd, rn, right_shift, fpcr_rounding);
5888 ucvtf(vf, rd, rn, right_shift, fpcr_rounding);
H A Dsimulator-arm64.h1894 LogicVRegister ucvtf(VectorFormat vform, LogicVRegister dst,
H A Dsimulator-logic-arm64.cc4211 LogicVRegister Simulator::ucvtf(VectorFormat vform, LogicVRegister dst, in ucvtf() function in v8::internal::Simulator
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc7157 ucvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
7239 ucvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
8828 ucvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
8921 ucvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
9390 ucvtf(vf, rd, rn, right_shift, fpcr_rounding); in Simulator()
9475 ucvtf(vf, rd, rn, right_shift, fpcr_rounding); in Simulator()
10907 ucvtf(vform, dst_data_size, src_data_size, zd, pg, zn, fpcr_rounding); in Simulator()
H A Dsimulator-aarch64.h4145 LogicVRegister ucvtf(VectorFormat vform,
4153 LogicVRegister ucvtf(VectorFormat vform,
H A Dassembler-aarch64.h2479 void ucvtf(const VRegister& fd, const Register& rn, int fbits = 0);
2485 void ucvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
5697 void ucvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
H A Dlogic-aarch64.cc6903 LogicVRegister Simulator::ucvtf(VectorFormat vform,
6947 LogicVRegister Simulator::ucvtf(VectorFormat vform,
6952 return ucvtf(vform,
H A Dmacro-assembler-aarch64.h2727 ucvtf(vd, rn, fbits); in Ucvtf()
3504 ucvtf(vd, vn, fbits); in Ucvtf()
6269 ucvtf(zd, pg, zn); in Ucvtf()
H A Dassembler-aarch64.cc3767 void Assembler::ucvtf(const VRegister& vd, const VRegister& vn, int fbits) {
3818 void Assembler::ucvtf(const VRegister& vd, const Register& rn, int fbits) {
H A Dassembler-sve-aarch64.cc1949 void Assembler::ucvtf(const ZRegister& zd, in ucvtf() function in vixl::aarch64::Assembler

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