| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | me_cmp_neon.S | 52 uaddlv s16, v16.8h // add up everything in v16 accumulator
168 uaddlv s4, v4.8h // finish adding up accumulated values
199 uaddlv s6, v6.8h // add up accumulator in v6
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| H A D | h264pred_neon.S | 56 uaddlv h0, v0.16b
65 uaddlv h0, v0.16b
76 uaddlv h0, v0.16b
77 uaddlv h1, v1.16b
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 2224 __ uaddlv(d28, v22.V4S()); in GenerateTestSequenceNEON()
2225 __ uaddlv(h0, v19.V16B()); in GenerateTestSequenceNEON()
2226 __ uaddlv(h30, v30.V8B()); in GenerateTestSequenceNEON()
2227 __ uaddlv(s24, v18.V4H()); in GenerateTestSequenceNEON()
2228 __ uaddlv(s10, v0.V8H()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2478 TEST_NEON(uaddlv_0, uaddlv(h0, v1.V8B()))
2479 TEST_NEON(uaddlv_1, uaddlv(h0, v1.V16B()))
2480 TEST_NEON(uaddlv_2, uaddlv(s0, v1.V4H()))
2481 TEST_NEON(uaddlv_3, uaddlv(s0, v1.V8H()))
2482 TEST_NEON(uaddlv_4, uaddlv(d0, v1.V4S()))
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| H A D | test-simulator-aarch64.cc | 4952 DEFINE_TEST_NEON_ACROSS_LONG(uaddlv, Basic)
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1197 void uaddlv(const VRegister& vd, const VRegister& vn);
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| H A D | macro-assembler-arm64.h | 315 V(uaddlv, Uaddlv) \
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| H A D | assembler-arm64.cc | 2025 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) { in uaddlv() function in v8::internal::Assembler
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1777 LogicVRegister uaddlv(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4653 uaddlv(vf, rd, rn);
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| H A D | simulator-logic-arm64.cc | 1201 LogicVRegister Simulator::uaddlv(VectorFormat vform, LogicVRegister dst, in uaddlv() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 3912 LogicVRegister uaddlv(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3049 void uaddlv(const VRegister& vd, const VRegister& vn);
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| H A D | assembler-aarch64.cc | 5339 void Assembler::uaddlv(const VRegister& vd, const VRegister& vn) {
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| H A D | logic-aarch64.cc | 1284 LogicVRegister Simulator::uaddlv(VectorFormat vform, in uaddlv() function in vixl::aarch64::Simulator
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| H A D | macro-assembler-aarch64.h | 3065 V(uaddlv, Uaddlv) \
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| H A D | simulator-aarch64.cc | 7938 uaddlv(vf, rd, rn); in Simulator()
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