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Searched refs:tileSwizzle (Results 1 - 4 of 4) sorted by relevance

/third_party/mesa3d/src/amd/addrlib/inc/
H A Daddrinterface.h716 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE member
804 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE member
1388 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE member
1460 UINT_32 tileSwizzle; ///< Combined swizzle, if useCombinedSwizzle is TRUE member
1634 UINT_32 tileSwizzle; ///< Combined swizzle member
1696 UINT_32 tileSwizzle; ///< Recalculated tileSwizzle value member
1787 UINT_32 tileSwizzle; ///< Combined swizzle member
2273 UINT_32 tileSwizzle; ///< Tile swizzle member
3261 UINT_32 tileSwizzle; ///< Combine member
3318 UINT_32 tileSwizzle; ///< Combined swizzle used to do bank/pipe rotation global() member
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/third_party/mesa3d/src/amd/addrlib/src/r800/
H A Degbaddrlib.cpp1403 ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
2268 ExtractBankPipeSwizzle(pIn->tileSwizzle, pIn->pTileInfo,
2774 return HwlCombineBankPipeSwizzle(bankSwizzle, pipeSwizzle, pTileInfo, 0, &pOut->tileSwizzle);
2833 UINT_32 tileSwizzle = pipeSwizzle + ((bankSwizzle << bankInterleaveBits) << pipeBits);
2835 baseAddr ^= tileSwizzle * m_pipeInterleaveBytes;
2858 UINT_32 tileSwizzle = 0;
2897 tileSwizzle = GetBankPipeSwizzle(bankSwizzle,
2903 return tileSwizzle;
3967 pOut->tileSwizzle = ComputeSliceTileSwizzle(pIn->tileMode,
/third_party/mesa3d/src/amd/common/
H A Dac_surface.c946 assert(AddrBaseSwizzleOut.tileSwizzle <= in gfx6_surface_settings()
948 surf->tile_swizzle = AddrBaseSwizzleOut.tileSwizzle; in gfx6_surface_settings()
1358 assert(xout.tileSwizzle <= u_bit_consecutive(0, sizeof(surf->tile_swizzle) * 8)); in gfx6_compute_surface()
1359 surf->fmask_tile_swizzle = xout.tileSwizzle; in gfx6_compute_surface()
/third_party/mesa3d/src/amd/addrlib/src/core/
H A Daddrlib1.cpp744 &pOut->tileSwizzle); in CombineBankPipeSwizzle()
800 pOut->tileSwizzle = 0; in ComputeBaseSwizzle()

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