Searched refs:tc_compatible_htile (Results 1 - 4 of 4) sorted by relevance
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_texture.c | 47 bool tc_compatible_htile);
176 bool is_flushed_depth, bool tc_compatible_htile) in si_init_surface()
200 } else if (tc_compatible_htile && in si_init_surface()
508 tex->tc_compatible_htile = new_tex->tc_compatible_htile; in si_reallocate_texture_inplace()
844 u_log_printf(log, ", tc_compatible_htile=%u", tex->tc_compatible_htile); in si_print_texture_info()
958 tex->tc_compatible_htile = (sscreen->info.gfx_level == GFX8 && in si_texture_create_object()
1068 if (sscreen->info.gfx_level >= GFX9 || tex->tc_compatible_htile) in si_texture_create_object()
1177 bool tc_compatible_htile) in si_choose_tiling()
173 si_init_surface(struct si_screen *sscreen, struct radeon_surf *surface, const struct pipe_resource *ptex, enum radeon_surf_mode array_mode, uint64_t modifier, bool is_imported, bool is_scanout, bool is_flushed_depth, bool tc_compatible_htile) si_init_surface() argument
1175 si_choose_tiling(struct si_screen *sscreen, const struct pipe_resource *templ, bool tc_compatible_htile) si_choose_tiling() argument
1262 bool tc_compatible_htile = si_texture_create_with_modifier() local
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| H A D | si_clear.c | 653 (!zstex->tc_compatible_htile || depth == 0 || depth == 1); in si_can_fast_clear_depth()
662 (!zstex->tc_compatible_htile || stencil == 0); in si_can_fast_clear_stencil()
922 assert(!zstex->tc_compatible_htile); in si_fast_clear()
926 zstex->tc_compatible_htile = true; in si_fast_clear()
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| H A D | si_pipe.h | 410 bool tc_compatible_htile : 1; member
1867 assert(!tex->tc_compatible_htile || tex->surface.meta_offset); in vi_tc_compat_htile_enabled()
1868 return tex->tc_compatible_htile && si_htile_enabled(tex, level, zs_mask); in vi_tc_compat_htile_enabled()
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| H A D | si_state.c | 3553 if (tex->tc_compatible_htile) { in si_emit_framebuffer_state()
3570 S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile)); in si_emit_framebuffer_state()
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