| /third_party/optimized-routines/string/aarch64/ |
| H A D | __mtag_tag_zero_region.S | 38 tbnz count, 6, L(set96)
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| H A D | __mtag_tag_region.S | 38 tbnz count, 6, L(set96)
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| H A D | memchr-mte.S | 78 tbnz tmp, 4, L(loop32_2)
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| H A D | memrchr.S | 79 tbnz tmp, 4, L(loop32_2)
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| H A D | memset.S | 56 tbnz count, 6, L(set96)
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| H A D | strnlen.S | 74 tbnz tmp, 4, L(loop32_2)
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| H A D | strncmp-mte.S | 240 tbnz offset, 6, L(misaligned_mid_loop)
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| /third_party/musl/src/string/aarch64/ |
| H A D | memset.S | 54 tbnz count, 6, .Lset96
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| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vc1dsp_neon.S | 767 tbnz w0, #0, 1f // none of the 4 pixel pairs should be updated if this one is not filtered
838 tbnz w2, #0, 1f // none of the 4 pixel pairs should be updated if this one is not filtered
918 tbnz w0, #0, 1f // none of the 8 pixel pairs should be updated in this case
1018 tbnz w5, #0, 2f // none of the 8 pixel pairs should be updated in this case
1024 tbnz w2, #0, 1f // none of the first 4 pixel pairs should be updated if so
1029 1: tbnz w3, #0, 2f // none of the second 4 pixel pairs should be updated if so
1158 tbnz w0, #0, 1f // none of the 16 pixel pairs should be updated in this case
1341 tbnz w9, #0, 4f // none of the 16 pixel pairs should be updated in this case
1349 tbnz w2, #0, 1f
1354 1: tbnz w
[all...] |
| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 407 void tbnz(const Register& rt, unsigned bit_pos, Label* label);
408 void tbnz(const Register& rt, unsigned bit_pos, int imm14);
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| H A D | macro-assembler-arm64.cc | 1038 tbnz(rt, bit_pos, label); in Tbnz()
1051 tbnz(rt, bit_pos, &done); in Tbz()
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| H A D | assembler-arm64.cc | 815 void Assembler::tbnz(const Register& rt, unsigned bit_pos, int imm14) { in tbnz() function in v8::internal::Assembler
820 void Assembler::tbnz(const Register& rt, unsigned bit_pos, Label* label) { in tbnz() function in v8::internal::Assembler
821 tbnz(rt, bit_pos, LinkAndGetInstructionOffsetTo(label)); in tbnz()
|
| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-aarch64.cc | 947 COMPARE_PREFIX(tbnz(w8, 0, INST_OFF(0x7ffc)), "tbnz w8, #0, #+0x7ffc"); in TEST()
948 COMPARE_PREFIX(tbnz(x9, 63, INST_OFF(-0x8000)), "tbnz x9, #63, #-0x8000"); in TEST()
949 COMPARE_PREFIX(tbnz(w10, 31, INST_OFF(0)), "tbnz w10, #31, #+0x0"); in TEST()
950 COMPARE_PREFIX(tbnz(x11, 31, INST_OFF(0x4)), "tbnz w11, #31, #+0x4"); in TEST()
951 COMPARE_PREFIX(tbnz(x12, 32, INST_OFF(0x8)), "tbnz x1 in TEST()
[all...] |
| H A D | test-cpu-features-aarch64.cc | 504 TEST_NONE(tbnz_0, tbnz(x0, 0, &label))
505 TEST_NONE(tbnz_1, tbnz(x0, 37, &label))
506 TEST_NONE(tbnz_2, tbnz(w0, 20, &label))
|
| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-aarch64.cc | 739 tbnz(rt, bit_pos, label); in Emit()
759 tbnz(rt, bit_pos, &done); in Emit()
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| H A D | assembler-aarch64.cc | 434 void Assembler::tbnz(const Register& rt, unsigned bit_pos, int64_t imm14) { in tbnz() function in vixl::aarch64::Assembler
440 void Assembler::tbnz(const Register& rt, unsigned bit_pos, Label* label) { in tbnz() function in vixl::aarch64::Assembler
443 tbnz(rt, bit_pos, static_cast<int>(offset)); in tbnz()
|
| H A D | assembler-aarch64.h | 644 void tbnz(const Register& rt, unsigned bit_pos, Label* label);
647 void tbnz(const Register& rt, unsigned bit_pos, int64_t imm14);
|