Searched refs:surf_info (Results 1 - 5 of 5) sorted by relevance
| /third_party/mesa3d/src/amd/vulkan/winsys/amdgpu/ |
| H A D | radv_amdgpu_surface.c | 38 radv_amdgpu_surface_sanity(const struct ac_surf_info *surf_info, const struct radeon_surf *surf) in radv_amdgpu_surface_sanity() argument
47 if (surf_info->height > 1) in radv_amdgpu_surface_sanity()
52 if (surf_info->depth > 1 || surf_info->array_size > 1) in radv_amdgpu_surface_sanity()
56 if (surf_info->array_size > 1) in radv_amdgpu_surface_sanity()
60 if (surf_info->height > 1) in radv_amdgpu_surface_sanity()
64 if (surf_info->depth > 1) in radv_amdgpu_surface_sanity()
74 radv_amdgpu_winsys_surface_init(struct radeon_winsys *_ws, const struct ac_surf_info *surf_info, in radv_amdgpu_winsys_surface_init() argument
81 r = radv_amdgpu_surface_sanity(surf_info, surf); in radv_amdgpu_winsys_surface_init()
90 memcpy(&config.info, surf_info, sizeo in radv_amdgpu_winsys_surface_init()
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| /third_party/mesa3d/src/intel/isl/ |
| H A D | isl.c | 1584 const struct isl_surf_init_info *surf_info, in isl_calc_row_pitch_alignment()
1599 isl_format_supports_ccs_e(dev->info, surf_info->format) && in isl_calc_row_pitch_alignment()
1601 !(surf_info->usage & ISL_SURF_USAGE_DISABLE_AUX_BIT) && in isl_calc_row_pitch_alignment()
1602 surf_info->row_pitch_B == 0) { in isl_calc_row_pitch_alignment()
1610 assert((surf_info->usage & ISL_SURF_USAGE_CPB_BIT) == 0); in isl_calc_row_pitch_alignment()
1626 const struct isl_format_layout *fmtl = isl_format_get_layout(surf_info->format); in isl_calc_row_pitch_alignment()
1630 if (surf_info->usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) { in isl_calc_row_pitch_alignment()
1631 if (isl_format_is_yuv(surf_info->format)) { in isl_calc_row_pitch_alignment()
1654 if (surf_info->usage & ISL_SURF_USAGE_DISPLAY_BIT) { in isl_calc_row_pitch_alignment()
1655 if (surf_info in isl_calc_row_pitch_alignment()
1583 isl_calc_row_pitch_alignment(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info) isl_calc_row_pitch_alignment() argument
1677 isl_calc_tiled_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, const struct isl_extent4d *phys_total_el, uint32_t alignment_B) isl_calc_tiled_min_row_pitch() argument
1701 isl_calc_min_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, const struct isl_extent4d *phys_total_el, uint32_t alignment_B) isl_calc_min_row_pitch() argument
1733 isl_calc_row_pitch(const struct isl_device *dev, const struct isl_surf_init_info *surf_info, const struct isl_tile_info *tile_info, enum isl_dim_layout dim_layout, const struct isl_extent4d *phys_total_el, uint32_t *out_row_pitch_B) isl_calc_row_pitch() argument
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| /third_party/mesa3d/src/amd/vulkan/ |
| H A D | radv_radeon_winsys.h | 302 int (*surface_init)(struct radeon_winsys *ws, const struct ac_surf_info *surf_info,
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| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_texture.c | 832 char *surf_info = NULL; in si_print_texture_info() local
849 f = open_memstream(&surf_info, &surf_info_size); in si_print_texture_info()
854 u_log_printf(log, "%s", surf_info); in si_print_texture_info()
855 free(surf_info); in si_print_texture_info()
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| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_surface.c | 170 ADDR2_COMPUTE_SURFACE_INFO_INPUT *surf_info) in ac_modifier_fill_dcc_params()
175 surf_info->flags.metaPipeUnaligned = 0; in ac_modifier_fill_dcc_params()
177 surf_info->flags.metaPipeUnaligned = !AMD_FMT_MOD_GET(DCC_PIPE_ALIGN, modifier); in ac_modifier_fill_dcc_params()
182 surf_info->flags.metaRbUnaligned = AMD_FMT_MOD_GET(TILE_VERSION, modifier) == AMD_FMT_MOD_TILE_VER_GFX9 && in ac_modifier_fill_dcc_params()
184 surf_info->flags.metaPipeUnaligned; in ac_modifier_fill_dcc_params()
169 ac_modifier_fill_dcc_params(uint64_t modifier, struct radeon_surf *surf, ADDR2_COMPUTE_SURFACE_INFO_INPUT *surf_info) ac_modifier_fill_dcc_params() argument
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