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Searched refs:subreg (Results 1 - 7 of 7) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
H A Dbrw_eu_validate.c950 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); in general_restrictions_based_on_operand_types() local
951 ERROR_IF(subreg % 4 != 0, in general_restrictions_based_on_operand_types()
957 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); in general_restrictions_based_on_operand_types() local
960 dst_stride == 1 && subreg % 16 == 0), in general_restrictions_based_on_operand_types()
984 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); in general_restrictions_based_on_operand_types() local
994 ERROR_IF(subreg % exec_type_size != 0 && in general_restrictions_based_on_operand_types()
995 subreg % exec_type_size != 1, in general_restrictions_based_on_operand_types()
996 "Destination subreg must be aligned to the size of the " in general_restrictions_based_on_operand_types()
1000 ERROR_IF(subreg % exec_type_size != 0, in general_restrictions_based_on_operand_types()
1001 "Destination subreg mus in general_restrictions_based_on_operand_types()
1074 unsigned vstride, width, hstride, element_size, subreg; general_restrictions_on_region_parameters() local
1329 unsigned subreg; special_restrictions_for_mixed_float_mode() local
1413 align1_access_mask(uint64_t access_mask[static 32], unsigned exec_size, unsigned element_size, unsigned subreg, unsigned vstride, unsigned width, unsigned hstride) align1_access_mask() argument
1484 unsigned vstride, width, hstride, element_size, subreg; region_alignment_rules() local
1533 unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst); region_alignment_rules() local
1876 unsigned vstride, width, hstride, type_size, reg, subreg, address_mode; special_requirements_for_handling_double_precision_data_types() local
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H A Dbrw_reg.h898 brw_flag_reg(int reg, int subreg)
901 BRW_ARF_FLAG + reg, subreg);
905 brw_flag_subreg(unsigned subreg)
908 BRW_ARF_FLAG + subreg / 2, subreg % 2);
H A Dbrw_eu.c172 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg) in brw_set_default_flag_reg() argument
174 assert(subreg < 2); in brw_set_default_flag_reg()
175 p->current->flag_subreg = reg * 2 + subreg; in brw_set_default_flag_reg()
H A Dbrw_mesh.cpp815 unsigned subreg; in get_mesh_urb_handle() local
817 subreg = 6; in get_mesh_urb_handle()
820 subreg = op == nir_intrinsic_load_task_payload ? 7 : 6; in get_mesh_urb_handle()
826 ubld8.MOV(h, retype(brw_vec1_grf(0, subreg), BRW_REGISTER_TYPE_UD)); in get_mesh_urb_handle()
H A Dbrw_lower_logical_sends.cpp1306 const unsigned subreg = sample_mask_flag_subreg(v); in emit_predicate_on_vector_mask() local
1308 ubld.MOV(brw_flag_subreg(subreg + inst->group / 16), vector_mask); in emit_predicate_on_vector_mask()
1319 inst->flag_subreg = subreg; in emit_predicate_on_vector_mask()
H A Dbrw_eu.h79 /* Flag subreg. Bottom bit is subreg, top bit is reg */
174 void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg);
H A Dbrw_fs.cpp4436 const unsigned subreg = sample_mask_flag_subreg(v);
4440 sample_mask.nr == brw_flag_subreg(subreg).nr &&
4442 subreg + inst->group / 16).subnr);
4445 .MOV(brw_flag_subreg(subreg + inst->group / 16), sample_mask);
4457 inst->flag_subreg = subreg;

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