| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | h264dsp_neon.S | 103 ssubw v22.8H, v22.8H, v4.8B
407 ssubw v22.8H, v22.8H, v4.8B
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| H A D | vp9lpf_neon.S | 118 ssubw \dst1, \in1, \in3\().8b
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1303 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 440 V(ssubw, Ssubw) \
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| H A D | assembler-arm64.cc | 1855 void Assembler::ssubw(const VRegister& vd, const VRegister& vn, in ssubw() function in v8::internal::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1799 __ ssubw(v25.V2D(), v23.V2D(), v26.V2S()); in GenerateTestSequenceNEON()
1800 __ ssubw(v21.V4S(), v18.V4S(), v24.V4H()); in GenerateTestSequenceNEON()
1801 __ ssubw(v30.V8H(), v22.V8H(), v3.V8B()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 2009 TEST_NEON(ssubw_0, ssubw(v0.V8H(), v1.V8H(), v2.V8B()))
2010 TEST_NEON(ssubw_1, ssubw(v0.V4S(), v1.V4S(), v2.V4H()))
2011 TEST_NEON(ssubw_2, ssubw(v0.V2D(), v1.V2D(), v2.V2S()))
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| H A D | test-simulator-aarch64.cc | 4730 DEFINE_TEST_NEON_3DIFF_WIDE(ssubw, Basic)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1853 LogicVRegister ssubw(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4570 ssubw(vf_l, rd, rn, rm);
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| H A D | simulator-logic-arm64.cc | 2455 LogicVRegister Simulator::ssubw(VectorFormat vform, LogicVRegister dst, in ssubw() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 2589 ssubw(vform, zd, zn, zm_b); in Simulator()
2592 ssubw(vform, zd, zn, zm_t); in Simulator()
7834 ssubw(vf_l, rd, rn, rm); in Simulator()
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| H A D | simulator-aarch64.h | 4059 LogicVRegister ssubw(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3177 void ssubw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | assembler-aarch64.cc | 3090 void Assembler::ssubw(const VRegister& vd,
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| H A D | logic-aarch64.cc | 3642 LogicVRegister Simulator::ssubw(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 2941 V(ssubw, Ssubw) \
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