/third_party/mesa3d/src/gallium/drivers/freedreno/ |
H A D | freedreno_draw.h | 45 enum pc_di_src_sel src_sel, uint32_t count, uint8_t instances, in fd_draw() 94 OUT_RING(ring, DRAW_A20X(primtype, DI_FACE_CULL_NONE, src_sel, idx_type, in fd_draw() 107 OUT_RINGP(ring, DRAW(primtype, src_sel, idx_type, 0, instances), in fd_draw() 110 OUT_RING(ring, DRAW(primtype, src_sel, idx_type, vismode, instances)); in fd_draw() 150 enum pc_di_src_sel src_sel; in fd_draw_emit() local 160 src_sel = DI_SRC_SEL_DMA; in fd_draw_emit() 166 src_sel = DI_SRC_SEL_AUTO_INDEX; in fd_draw_emit() 169 fd_draw(batch, ring, primtype, vismode, src_sel, draw->count, in fd_draw_emit() 43 fd_draw(struct fd_batch *batch, struct fd_ringbuffer *ring, enum pc_di_primtype primtype, enum pc_di_vis_cull_mode vismode, enum pc_di_src_sel src_sel, uint32_t count, uint8_t instances, enum pc_di_index_size idx_type, uint32_t idx_size, uint32_t idx_offset, struct pipe_resource *idx_buffer) fd_draw() argument
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/third_party/mesa3d/src/gallium/drivers/freedreno/a5xx/ |
H A D | fd5_draw.h | 45 enum pc_di_src_sel src_sel, uint32_t count, uint32_t instances, in fd5_draw() 62 OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0), in fd5_draw() 65 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode)); in fd5_draw() 89 enum pc_di_src_sel src_sel; in fd5_draw_emit() local 129 src_sel = DI_SRC_SEL_DMA; in fd5_draw_emit() 135 src_sel = DI_SRC_SEL_AUTO_INDEX; in fd5_draw_emit() 138 fd5_draw(batch, ring, primtype, vismode, src_sel, draw->count, in fd5_draw_emit() 43 fd5_draw(struct fd_batch *batch, struct fd_ringbuffer *ring, enum pc_di_primtype primtype, enum pc_di_vis_cull_mode vismode, enum pc_di_src_sel src_sel, uint32_t count, uint32_t instances, enum a4xx_index_size idx_type, uint32_t max_indices, uint32_t idx_offset, struct pipe_resource *idx_buffer) fd5_draw() argument
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/third_party/mesa3d/src/gallium/drivers/freedreno/a4xx/ |
H A D | fd4_draw.h | 51 enum pc_di_src_sel src_sel, uint32_t count, uint32_t instances, in fd4_draw() 68 OUT_RINGP(ring, DRAW4(primtype, src_sel, idx_type, 0), in fd4_draw() 71 OUT_RING(ring, DRAW4(primtype, src_sel, idx_type, vismode)); in fd4_draw() 95 enum pc_di_src_sel src_sel; in fd4_draw_emit() local 135 src_sel = DI_SRC_SEL_DMA; in fd4_draw_emit() 141 src_sel = DI_SRC_SEL_AUTO_INDEX; in fd4_draw_emit() 144 fd4_draw(batch, ring, primtype, vismode, src_sel, draw->count, in fd4_draw_emit() 49 fd4_draw(struct fd_batch *batch, struct fd_ringbuffer *ring, enum pc_di_primtype primtype, enum pc_di_vis_cull_mode vismode, enum pc_di_src_sel src_sel, uint32_t count, uint32_t instances, enum a4xx_index_size idx_type, uint32_t max_indices, uint32_t idx_offset, struct pipe_resource *idx_buffer) fd4_draw() argument
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/third_party/mesa3d/src/gallium/drivers/r600/sb/ |
H A D | sb_bc_builder.cpp | 556 .SRC_SEL_X(bc.src_sel[0]) in build_fetch_tex() 557 .SRC_SEL_Y(bc.src_sel[1]) in build_fetch_tex() 558 .SRC_SEL_Z(bc.src_sel[2]) in build_fetch_tex() 559 .SRC_SEL_W(bc.src_sel[3]); in build_fetch_tex() 581 .SRC_SEL_X(bc.src_sel[0]) in build_fetch_gds() 582 .SRC_SEL_Y(bc.src_sel[1]) in build_fetch_gds() 583 .SRC_SEL_Z(bc.src_sel[2]); in build_fetch_gds() 619 .SRC_SEL_X(bc.src_sel[0]) in build_fetch_vtx() 631 .SRC_SEL_X(bc.src_sel[0]) in build_fetch_vtx() 632 .SRC_SEL_Y(bc.src_sel[ in build_fetch_vtx() [all...] |
H A D | sb_bc_decoder.cpp | 491 bc.src_sel[0] = w2.get_SRC_SEL_X(); in decode_fetch() 492 bc.src_sel[1] = w2.get_SRC_SEL_Y(); in decode_fetch() 493 bc.src_sel[2] = w2.get_SRC_SEL_Z(); in decode_fetch() 494 bc.src_sel[3] = w2.get_SRC_SEL_W(); in decode_fetch() 514 bc.src_sel[0] = w0.get_SRC_SEL_X(); in decode_fetch_gds() 515 bc.src_sel[1] = w0.get_SRC_SEL_Y(); in decode_fetch_gds() 516 bc.src_sel[2] = w0.get_SRC_SEL_Z(); in decode_fetch_gds() 551 bc.src_sel[1] = w0.get_SRC_SEL_Y(); in decode_fetch_mem() 554 bc.src_sel[0] = w0.get_SRC_SEL_X(); in decode_fetch_mem() 594 bc.src_sel[ in decode_fetch_vtx() [all...] |
H A D | sb_bc_finalize.cpp | 537 dst.bc.src_sel[chan] = sel; in copy_fetch_src() 600 unsigned sel = f->bc.src_sel[chan]; in finalize_fetch() 644 f->bc.src_sel[chan] = sel; in finalize_fetch()
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H A D | sb_bc_parser.cpp | 696 unsigned sw = n->bc.src_sel[s]; in prepare_fetch_clause() 727 if (n->bc.src_sel[s] <= SEL_W) in prepare_fetch_clause() 729 n->bc.src_sel[s], false); in prepare_fetch_clause() 819 assert(!"invalid src_sel for export"); in prepare_ir()
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H A D | sb_bc_dump.cpp | 505 s << chans[n.bc.src_sel[k]]; in dump()
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H A D | sb_bc.h | 579 unsigned src_sel[4]; member
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/third_party/mesa3d/src/gallium/drivers/radeonsi/ |
H A D | si_cp_dma.c | 471 struct si_resource *dst, unsigned dst_offset, unsigned src_sel, in si_cp_copy_data() 487 radeon_emit(COPY_DATA_SRC_SEL(src_sel) | COPY_DATA_DST_SEL(dst_sel) | COPY_DATA_WR_CONFIRM); in si_cp_copy_data() 470 si_cp_copy_data(struct si_context *sctx, struct radeon_cmdbuf *cs, unsigned dst_sel, struct si_resource *dst, unsigned dst_offset, unsigned src_sel, struct si_resource *src, unsigned src_offset) si_cp_copy_data() argument
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H A D | si_pipe.h | 1455 struct si_resource *dst, unsigned dst_offset, unsigned src_sel,
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/third_party/mesa3d/src/gallium/drivers/nouveau/nvc0/ |
H A D | nvc0_query_hw_sm.c | 601 uint32_t src_sel; /* signal selection for up to 4 sources */ member 2374 PUSH_DATA (push, cfg->ctr[i].src_sel + 0x2108421 * (c & 3)); in nve4_hw_sm_begin_query() 2455 PUSH_DATA (push, cfg->ctr[i].src_sel | mask_sel); in nvc0_hw_sm_begin_query()
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/third_party/mesa3d/src/freedreno/vulkan/ |
H A D | tu_cmd_buffer.c | 4561 tu_draw_initiator(struct tu_cmd_buffer *cmd, enum pc_di_src_sel src_sel) in tu_draw_initiator() argument 4581 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel) | in tu_draw_initiator()
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