Searched refs:src1_reg (Results 1 - 8 of 8) sorted by relevance
| /third_party/mesa3d/src/amd/compiler/ |
| H A D | aco_lower_to_hw_instr.cpp | 199 emit_int64_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, in emit_int64_dpp_op() argument
207 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}; in emit_int64_dpp_op()
208 Operand src1_64 = Operand(src1_reg, v2); in emit_int64_dpp_op()
299 emit_int64_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, in emit_int64_op() argument
306 Operand src1[] = {Operand(src1_reg, v1), Operand(PhysReg{src1_reg + 1}, v1)}; in emit_int64_op()
308 Operand src1_64 = Operand(src1_reg, v2); in emit_int64_op()
356 if (src1_reg == dst_reg) { in emit_int64_op()
358 std::swap(src0_reg, src1_reg); in emit_int64_op()
386 emit_dpp_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, ReduceOp op, unsigned size, unsigned dpp_ctrl, unsigned row_mask, unsigned bank_mask, bool bound_ctrl, Operand* identity = NULL) emit_dpp_op() argument
427 emit_op(lower_context* ctx, PhysReg dst_reg, PhysReg src0_reg, PhysReg src1_reg, PhysReg vtmp, ReduceOp op, unsigned size) emit_op() argument
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| /third_party/mesa3d/src/gallium/drivers/etnaviv/ |
| H A D | etnaviv_disasm.c | 64 uint32_t src1_reg : 9; member
568 .reg = instr->src1_reg, in print_instr()
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| /third_party/mesa3d/src/freedreno/ir2/ |
| H A D | instr-a2xx.h | 159 uint8_t src1_reg : 6; member
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| H A D | disasm-a2xx.c | 261 print_srcreg(alu->src1_reg, alu->src1_sel, alu->src1_swiz, in disasm_alu()
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| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | disassemble.c | 850 if (reg_info->src1_reg == REGISTER_CONSTANT) in print_vector_field()
854 print_vector_src(ctx, fp, alu_field->src1, mode, reg_info->src1_reg, in print_vector_field()
945 if (reg_info->src1_reg == REGISTER_CONSTANT) in print_scalar_field()
948 print_scalar_src(ctx, fp, is_int, alu_field->src1, reg_info->src1_reg); in print_scalar_field()
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| H A D | midgard.h | 350 unsigned src1_reg : 5; member
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| H A D | midgard_emit.c | 859 .src1_reg = (ins->src[0] == ~0 ? in emit_alu_bundle()
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| /third_party/pcre2/pcre2/src/sljit/ |
| H A D | sljitNativeARM_32.c | 1905 sljit_s32 src1_reg; in emit_op() local
1992 src1_reg = src1; in emit_op()
1995 src1_reg = TMP_REG1; in emit_op()
1999 src1_reg = TMP_REG1; in emit_op()
2030 FAIL_IF(emit_single_op(compiler, op, flags, (sljit_uw)dst_reg, (sljit_uw)src1_reg, (sljit_uw)src2_reg)); in emit_op()
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