| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | vp9mc_16bpp_neon.S | 211 sqrshrun2 v1.8h, v2.4s, #7
212 sqrshrun2 v24.8h, v25.4s, #7
218 sqrshrun2 v2.8h, v4.4s, #7
219 sqrshrun2 v25.8h, v27.4s, #7
357 sqrshrun2 \reg1\().8h, \reg2\().4s, #7
359 sqrshrun2 \reg2\().8h, \reg4\().4s, #7
361 sqrshrun2 \reg3\().8h, \reg6\().4s, #7
363 sqrshrun2 \reg4\().8h, \reg8\().4s, #7
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| H A D | vp9mc_neon.S | 287 sqrshrun2 v1.16b, v2.8h, #7
288 sqrshrun2 v24.16b, v25.8h, #7
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| H A D | vp8dsp_neon.S | 770 sqrshrun2 \d0\().16b, v22.8h, #7
834 sqrshrun2 \d0\().16b, \s2\().8h, #7
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1417 void sqrshrun2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | macro-assembler-arm64.h | 1226 V(sqrshrun2, Sqrshrun2) \
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| H A D | assembler-arm64.cc | 1794 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) { in sqrshrun2() function in v8::internal::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1642 __ sqrshrun2(v24.V16B(), v0.V8H(), 8); in GenerateTestSequenceNEON()
1643 __ sqrshrun2(v22.V4S(), v1.V2D(), 23); in GenerateTestSequenceNEON()
1644 __ sqrshrun2(v28.V8H(), v21.V4S(), 13); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1849 TEST_NEON(sqrshrun2_0, sqrshrun2(v0.V16B(), v1.V8H(), 1))
1850 TEST_NEON(sqrshrun2_1, sqrshrun2(v0.V8H(), v1.V4S(), 7))
1851 TEST_NEON(sqrshrun2_2, sqrshrun2(v0.V4S(), v1.V2D(), 29))
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1987 LogicVRegister sqrshrun2(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 5963 sqrshrun2(vf, rd, rn, right_shift);
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| H A D | simulator-logic-arm64.cc | 2312 LogicVRegister Simulator::sqrshrun2(VectorFormat vform, LogicVRegister dst, in sqrshrun2() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.h | 4328 LogicVRegister sqrshrun2(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3288 void sqrshrun2(const VRegister& vd, const VRegister& vn, int shift);
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| H A D | assembler-aarch64.cc | 5766 void Assembler::sqrshrun2(const VRegister& vd, const VRegister& vn, int shift) {
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| H A D | logic-aarch64.cc | 3468 LogicVRegister Simulator::sqrshrun2(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 3169 V(sqrshrun2, Sqrshrun2) \
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| H A D | simulator-aarch64.cc | 9550 sqrshrun2(vf, rd, rn, right_shift); in Simulator()
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