| /third_party/vixl/test/aarch64/ |
| H A D | test-api-movprfx-aarch64.cc | 2229 __ sqrdmlsh(z11.VnB(), z16.VnB(), z31.VnB()); in TEST()
2232 __ sqrdmlsh(z11.VnH(), z16.VnH(), z1.VnH(), 0); in TEST()
2235 __ sqrdmlsh(z11.VnS(), z16.VnS(), z1.VnS(), 0); in TEST()
2238 __ sqrdmlsh(z11.VnD(), z16.VnD(), z1.VnD(), 0); in TEST()
3066 __ sqrdmlsh(z11.VnB(), z16.VnB(), z31.VnB()); in TEST()
3069 __ sqrdmlsh(z11.VnH(), z16.VnH(), z1.VnH(), 0); in TEST()
3072 __ sqrdmlsh(z11.VnS(), z16.VnS(), z1.VnS(), 0); in TEST()
3075 __ sqrdmlsh(z11.VnD(), z16.VnD(), z1.VnD(), 0); in TEST()
3419 __ sqrdmlsh(z11.VnB(), z16.VnB(), z11.VnB()); in TEST()
3422 __ sqrdmlsh(z1 in TEST()
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| H A D | test-cpu-features-aarch64.cc | 3431 TEST_RDM_NEON(sqrdmlsh_0, sqrdmlsh(v0.V4H(), v1.V4H(), v2.H(), 5))
3432 TEST_RDM_NEON(sqrdmlsh_1, sqrdmlsh(v0.V8H(), v1.V8H(), v2.H(), 5))
3433 TEST_RDM_NEON(sqrdmlsh_2, sqrdmlsh(v0.V2S(), v1.V2S(), v2.S(), 2))
3434 TEST_RDM_NEON(sqrdmlsh_3, sqrdmlsh(v0.V4S(), v1.V4S(), v2.S(), 1))
3435 TEST_RDM_NEON(sqrdmlsh_4, sqrdmlsh(h0, h1, v2.H(), 6))
3436 TEST_RDM_NEON(sqrdmlsh_5, sqrdmlsh(s0, s1, v2.S(), 1))
3437 TEST_RDM_NEON(sqrdmlsh_6, sqrdmlsh(v0.V4H(), v1.V4H(), v2.V4H()))
3438 TEST_RDM_NEON(sqrdmlsh_7, sqrdmlsh(v0.V8H(), v1.V8H(), v2.V8H()))
3439 TEST_RDM_NEON(sqrdmlsh_8, sqrdmlsh(v0.V2S(), v1.V2S(), v2.V2S()))
3440 TEST_RDM_NEON(sqrdmlsh_9, sqrdmlsh(v
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| H A D | test-simulator-aarch64.cc | 4660 DEFINE_TEST_NEON_3SAME_HS(sqrdmlsh, Basic)
4709 DEFINE_TEST_NEON_3SAME_SCALAR_HS(sqrdmlsh, Basic)
4981 DEFINE_TEST_NEON_BYELEMENT(sqrdmlsh, Basic, Basic, Basic)
5002 DEFINE_TEST_NEON_BYELEMENT_SCALAR(sqrdmlsh, Basic, Basic, Basic)
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| H A D | test-disasm-sve-aarch64.cc | 6966 COMPARE(sqrdmlsh(z11.VnB(), z16.VnB(), z31.VnB()), in TEST()
6967 "sqrdmlsh z11.b, z16.b, z31.b"); in TEST()
6968 COMPARE(sqrdmlsh(z11.VnD(), z16.VnD(), z31.VnD()), in TEST()
6969 "sqrdmlsh z11.d, z16.d, z31.d"); in TEST()
6970 COMPARE(sqrdmlsh(z11.VnH(), z16.VnH(), z31.VnH()), in TEST()
6971 "sqrdmlsh z11.h, z16.h, z31.h"); in TEST()
6972 COMPARE(sqrdmlsh(z11.VnS(), z16.VnS(), z31.VnS()), in TEST()
6973 "sqrdmlsh z11.s, z16.s, z31.s"); in TEST()
6985 "sqrdmlsh z23.s, z26.s, z29.s"); in TEST()
6987 "sqrdmlsh z3 in TEST()
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 1837 V(Sqrdmlsh, sqrdmlsh, FourRegDestructiveHelper) \
1873 V(Sqrdmlsh, sqrdmlsh, FourRegOneImmDestructiveHelper) \
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| H A D | assembler-aarch64.h | 3413 void sqrdmlsh(const VRegister& vd, const VRegister& vn, const VRegister& vm);
3448 void sqrdmlsh(const VRegister& vd,
6442 void sqrdmlsh(const ZRegister& zda,
6449 void sqrdmlsh(const ZRegister& zda, const ZRegister& zn, const ZRegister& zm);
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| H A D | simulator-aarch64.h | 3584 LogicVRegister sqrdmlsh(VectorFormat vform,
4391 LogicVRegister sqrdmlsh(VectorFormat vform,
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| H A D | simulator-aarch64.cc | 3007 sqrdmlsh(vform, zda, zn, (index >= 0) ? zm_idx : zm); in Simulator()
7691 sqrdmlsh(vf, rd, rn, rm); in Simulator()
8162 sqrdmlsh(vform, rd, rn, rm, index); in Simulator()
9147 sqrdmlsh(vf, rd, rn, rm); in Simulator()
9193 Op = &Simulator::sqrdmlsh; in Simulator()
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| H A D | logic-aarch64.cc | 888 LogicVRegister Simulator::sqrdmlsh(VectorFormat vform, in sqrdmlsh() function in vixl::aarch64::Simulator
895 return sqrdmlsh(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqrdmlsh()
4225 LogicVRegister Simulator::sqrdmlsh(VectorFormat vform,
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| H A D | assembler-aarch64.cc | 4353 void Assembler::sqrdmlsh(const VRegister& vd,
4768 V(sqrdmlsh, NEON_SQRDMLSH_byelement)
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| H A D | assembler-sve-aarch64.cc | 8375 void Assembler::sqrdmlsh(const ZRegister& zda, in sqrdmlsh() function in vixl::aarch64::Assembler
8397 void Assembler::sqrdmlsh(const ZRegister& zda, in sqrdmlsh() function in vixl::aarch64::Assembler
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| H A D | macro-assembler-aarch64.h | 2932 V(sqrdmlsh, Sqrdmlsh) \
3122 V(sqrdmlsh, Sqrdmlsh) \
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