Searched refs:sqincp (Results 1 - 5 of 5) sorted by relevance
| /third_party/vixl/test/aarch64/ |
| H A D | test-disasm-sve-aarch64.cc | 2041 COMPARE(sqincp(x26, p5.VnB(), w26), "sqincp x26, p5.b, w26"); in TEST()
2042 COMPARE(sqincp(x26, p5.VnH(), w26), "sqincp x26, p5.h, w26"); in TEST()
2043 COMPARE(sqincp(x26, p5.VnS(), w26), "sqincp x26, p5.s, w26"); in TEST()
2044 COMPARE(sqincp(x26, p5.VnD(), w26), "sqincp x26, p5.d, w26"); in TEST()
2045 COMPARE(sqincp(x5, p15.VnB()), "sqincp x in TEST()
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| H A D | test-api-movprfx-aarch64.cc | 1197 __ sqincp(z4.VnD(), p7); in TEST()
1591 __ sqincp(z7.VnS(), p6); in TEST()
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| /third_party/vixl/src/aarch64/ |
| H A D | assembler-aarch64.h | 5470 void sqincp(const Register& xd,
5475 void sqincp(const Register& xdn, const PRegisterWithLaneSize& pg);
5478 void sqincp(const ZRegister& zdn, const PRegister& pg);
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| H A D | assembler-sve-aarch64.cc | 2111 void Assembler::sqincp(const Register& xd, in sqincp() function in vixl::aarch64::Assembler
2126 void Assembler::sqincp(const Register& xdn, const PRegisterWithLaneSize& pg) { in sqincp() function in vixl::aarch64::Assembler
2138 void Assembler::sqincp(const ZRegister& zdn, const PRegister& pg) { in sqincp() function in vixl::aarch64::Assembler
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| H A D | macro-assembler-aarch64.h | 6010 sqincp(xdn, pg, wdn); in Sqincp()
6015 sqincp(xdn, pg); in Sqincp()
6020 // `sqincp` writes every lane, so use an unpredicated movprfx. in Sqincp()
6022 sqincp(zd, pg); in Sqincp()
6419 // `sqincp` writes every lane, so use an unpredicated movprfx. in Uqincp()
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