| /third_party/vixl/test/aarch64/ |
| H A D | test-simulator-aarch64.cc | 4740 DEFINE_TEST_NEON_3DIFF_LONG_SD(sqdmull, Basic)
4758 DEFINE_TEST_NEON_3DIFF_SCALAR_LONG_SD(sqdmull, Basic)
4977 DEFINE_TEST_NEON_BYELEMENT_DIFF(sqdmull, Basic, Basic, Basic)
4998 DEFINE_TEST_NEON_BYELEMENT_DIFF_SCALAR(sqdmull, Basic, Basic, Basic)
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| H A D | test-trace-aarch64.cc | 1581 __ sqdmull(d25, s2, s26); in GenerateTestSequenceNEON()
1582 __ sqdmull(d30, s14, v5.S(), 1); in GenerateTestSequenceNEON()
1583 __ sqdmull(s29, h18, h11); in GenerateTestSequenceNEON()
1584 __ sqdmull(s11, h13, v7.H(), 6); in GenerateTestSequenceNEON()
1585 __ sqdmull(v23.V2D(), v9.V2S(), v8.V2S()); in GenerateTestSequenceNEON()
1586 __ sqdmull(v18.V2D(), v29.V2S(), v4.S(), 1); in GenerateTestSequenceNEON()
1587 __ sqdmull(v17.V4S(), v24.V4H(), v7.V4H()); in GenerateTestSequenceNEON()
1588 __ sqdmull(v8.V4S(), v15.V4H(), v5.H(), 1); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1791 TEST_NEON(sqdmull_0, sqdmull(v0.V4S(), v1.V4H(), v2.H(), 1))
1792 TEST_NEON(sqdmull_1, sqdmull(v0.V2D(), v1.V2S(), v2.S(), 3))
1795 TEST_NEON(sqdmull_2, sqdmull(s0, h1, v2.H(), 2))
1796 TEST_NEON(sqdmull_3, sqdmull(d0, s1, v2.S(), 1))
1797 TEST_NEON(sqdmull_4, sqdmull(v0.V4S(), v1.V4H(), v2.V4H()))
1798 TEST_NEON(sqdmull_5, sqdmull(v0.V2D(), v1.V2S(), v2.V2S()))
1801 TEST_NEON(sqdmull_6, sqdmull(s0, h1, h2))
1802 TEST_NEON(sqdmull_7, sqdmull(d0, s1, s2))
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1039 void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm,
1111 void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 224 V(sqdmull, Sqdmull) \
429 V(sqdmull, Sqdmull) \
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| H A D | assembler-arm64.cc | 1503 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
3356 V(sqdmull, NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD()) \
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 2332 sqdmull(vform, zd, zn_b, zm_idx); in Simulator()
2335 sqdmull(vform, zd, zn_t, zm_idx); in Simulator()
2346 sqdmull(vform, zd, zn_b, zm_idx); in Simulator()
2349 sqdmull(vform, zd, zn_t, zm_idx); in Simulator()
2847 sqdmull(vform, zd, zn_b, zm_b); in Simulator()
2850 sqdmull(vform, zd, zn_t, zm_t); in Simulator()
7810 sqdmull(vf_l, rd, rn, rm); in Simulator()
7988 sqdmull(vf, rd, rn, temp, is_2); in Simulator()
8972 sqdmull(vf, rd, rn, rm); in Simulator()
9172 Op = &Simulator::sqdmull; in Simulator()
[all...] |
| H A D | logic-aarch64.cc | 822 LogicVRegister Simulator::sqdmull(VectorFormat vform, in sqdmull() function in vixl::aarch64::Simulator
830 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmull()
3892 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3911 LogicVRegister product = sqdmull(vform, temp, src1, src2, is_2);
3924 LogicVRegister Simulator::sqdmull(VectorFormat vform,
3939 return sqdmull(vform, dst, src1, src2, /* is_2 = */ true);
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| H A D | simulator-aarch64.h | 3554 LogicVRegister sqdmull(VectorFormat vform,
4461 V(sqdmull)
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| H A D | assembler-aarch64.h | 2641 void sqdmull(const VRegister& vd,
3375 void sqdmull(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | assembler-aarch64.cc | 2997 V(sqdmull, NEON_SQDMULL, vn.Is1H() || vn.Is1S() || vn.Is4H() || vn.Is2S()) \
4806 V(sqdmull, NEON_SQDMULL_byelement, vn.IsScalar() || vn.IsD()) \
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| H A D | macro-assembler-aarch64.h | 2926 V(sqdmull, Sqdmull) \
3123 V(sqdmull, Sqdmull) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-logic-arm64.cc | 843 LogicVRegister Simulator::sqdmull(VectorFormat vform, LogicVRegister dst, in sqdmull() function in v8::internal::Simulator
849 return sqdmull(vform, dst, src1, dup_element(indexform, temp, src2, index)); in sqdmull()
2677 LogicVRegister product = sqdmull(vform, temp, src1, src2); in sqdmlal()
2693 LogicVRegister product = sqdmull(vform, temp, src1, src2); in sqdmlsl()
2705 LogicVRegister Simulator::sqdmull(VectorFormat vform, LogicVRegister dst, in sqdmull() function in v8::internal::Simulator
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| H A D | simulator-arm64.h | 1666 LogicVRegister sqdmull(VectorFormat vform, LogicVRegister dst,
2030 V(sqdmull) \
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| H A D | simulator-arm64.cc | 4546 sqdmull(vf_l, rd, rn, rm);
4745 Op = &Simulator::sqdmull;
5490 sqdmull(vf, rd, rn, rm);
5630 Op = &Simulator::sqdmull;
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