| /third_party/mesa3d/src/broadcom/compiler/ |
| H A D | vir.c | 856 prog_data->tmu_spills = c->spills; in v3d_set_prog_data()
1669 "%d uniforms, %d max-temps, %d:%d spills:fills, " in v3d_shaderdb_dump()
1677 c->spills, in v3d_shaderdb_dump()
1828 /* If we compiled without spills, choose this. in v3d_compile()
1830 * have a very low cap on the allowed TMU spills so we assume in v3d_compile()
1831 * it will be better than a 2-thread compile without spills). in v3d_compile()
1836 if (c->spills == 0 || in v3d_compile()
1840 } else if (c->spills + c->fills < in v3d_compile()
1843 best_spill_fill_count = c->spills + c->fills; in v3d_compile()
1850 "spills an in v3d_compile()
[all...] |
| H A D | vir_register_allocate.c | 303 * penalize spills during that time. in v3d_choose_spill_node()
347 /* We fill the node priority after we are done inserting spills */ in add_node()
440 /* We always enable per-quad on spills/fills to ensure we spill in v3d_emit_spill_tmua()
475 * spilled temp except for postponed spills). Something that ends at ip in v3d_emit_spill_tmua()
532 c->spills++; in v3d_emit_tmu_spill()
673 /* spills */ in v3d_spill_reg()
941 return c->spills + c->fills < c->max_tmu_spills; in tmu_spilling_allowed()
1192 if (c->spills + c->fills > c->max_tmu_spills) in v3d_register_allocate()
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| H A D | nir_to_vir.c | 4469 * if we need to do any spills that inject additional thread switches later on,
4644 assert(c->spills + c->fills <= c->max_tmu_spills); in v3d_nir_to_vir()
4678 c->spills = 0; in v3d_nir_to_vir()
4689 if (!c->spills && c->last_thrsw != restore_last_thrsw) in v3d_nir_to_vir()
4692 if (c->spills && in v3d_nir_to_vir()
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| H A D | v3d_compiler.h | 699 * TMU spills.
714 * spills.
735 /* Whether TMU spills are allowed. If this is disabled it may cause
738 * eliminate TMU spills in the shader.
798 uint32_t spills, fills, loops;
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| /third_party/mesa3d/src/asahi/compiler/ |
| H A D | agx_compiler.h | 414 unsigned spills; member
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| H A D | agx_compile.c | 1340 "%u loops, %u:%u spills:fills\n", in agx_print_stats()
1344 ctx->spills, ctx->fills); in agx_print_stats()
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| /third_party/mesa3d/src/panfrost/midgard/ |
| H A D | compiler.h | 255 /* Count of spills and fills for shaderdb */
256 unsigned spills; member
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| H A D | midgard_ra.c | 1019 ctx->spills++; in mir_spill_register()
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| H A D | midgard_compile.c | 3374 "%u:%u spills:fills\n", in midgard_compile_shader_nir()
3381 ctx->spills, ctx->fills); in midgard_compile_shader_nir()
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| /third_party/mesa3d/src/intel/compiler/ |
| H A D | brw_compiler.h | 1544 uint32_t spills; member
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| H A D | brw_vec4_generator.cpp | 1528 /* `send_count` explicitly does not include spills or fills, as we'd in generate_code()
2235 "spills:fills, %u sends. Compacted %d to %d bytes (%.0f%%)\n", in generate_code()
2253 "%d:%d spills:fills, %u sends, " in generate_code()
2264 stats->spills = spill_count; in generate_code()
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| H A D | brw_fs_generator.cpp | 2537 /* `send_count` explicitly does not include spills or fills, as we'd in generate_code()
2570 "%d:%d spills:fills, %u sends, " in generate_code()
2604 "%d:%d spills:fills, %u sends, " in generate_code()
2623 stats->spills = shader_stats.spill_count; in generate_code()
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| /third_party/mesa3d/src/panfrost/bifrost/ |
| H A D | bi_ra.c | 684 ctx->spills++; in bi_spill_register()
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| H A D | compiler.h | 816 unsigned spills; member
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| H A D | bifrost_compile.c | 4195 ralloc_asprintf_append(&str, ", %u loops, %u:%u spills:fills\n", in bi_print_stats()
4196 ctx->loop_count, ctx->spills, ctx->fills); in bi_print_stats()
4244 "%u:%u spills:fills\n", in va_print_stats()
4249 ctx->loop_count, ctx->spills, ctx->fills); in va_print_stats()
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| /third_party/libunwind/libunwind/doc/ |
| H A D | libunwind-dynamic.tex | 337 spills register \Var{reg} to a frame-pointer-relative location. The
343 spills register \Var{reg} to a stack-pointer-relative location. The
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| /third_party/node/deps/v8/src/wasm/baseline/ |
| H A D | liftoff-assembler.cc | 552 ZoneVector<int>* slots, LiftoffRegList* spills, in GetTaggedSlotsForOOLCode()
558 // Registers get spilled just before the call to the runtime. In {spills} in GetTaggedSlotsForOOLCode()
561 spills->set(slot.reg()); in GetTaggedSlotsForOOLCode()
1191 // Fill return frame slots first to ensure that all potential spills happen in MoveToReturnLocations()
551 GetTaggedSlotsForOOLCode( ZoneVector<int>* slots, LiftoffRegList* spills, SpillLocation spill_location) GetTaggedSlotsForOOLCode() argument
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| H A D | liftoff-compiler.cc | 414 LiftoffRegList spills; member
704 &safepoint_info->slots, &safepoint_info->spills, in StackCheck()
753 &safepoint_info->slots, &safepoint_info->spills, in TierupCheck()
983 ool->safepoint_info->spills, index); in GenerateOutOfLineCode()
2781 &safepoint_info->slots, &safepoint_info->spills,
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| H A D | liftoff-assembler.h | 212 // {spills} contains all registers that contain references. The
219 /*out*/ LiftoffRegList* spills,
1561 // The amount of memory needed for register spills in OOL code.
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| /third_party/skia/src/core/ |
| H A D | SkVM.cpp | 3429 // We want to find a block of N adjacent registers requiring the fewest spills.
3433 int spills = 0;
3443 spills = 0x7fff'ffff;
3449 spills += needs_spill(v) ? 1 : 0;
3453 if (min_spills > spills) {
3454 min_spills = spills;
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| /third_party/ffmpeg/libavcodec/x86/ |
| H A D | vp9itxfm_16bpp.asm | 1276 ; r65-69 are available for spills
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| /third_party/mesa3d/src/intel/vulkan/ |
| H A D | anv_pipeline.c | 3121 stat->value.u64 = exe->stats.spills; in anv_GetPipelineExecutableStatisticsKHR()
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