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Searched refs:spill (Results 1 - 25 of 36) sorted by relevance

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/third_party/libunwind/libunwind/src/ia64/
H A Dgetcontext.S51 st8.spill [r2] = r1, (SC_FLAGS - GR(1)) // M3
66 st8.spill [r2] = r12, (GR(4) - GR(12)) // M3
70 stf.spill [r3] = f2 // M2
71 stf.spill [r8] = f16 // M3
76 stf.spill [r9] = f24, (FR(31) - FR(24)) // M2
80 stf.spill [r9] = f31 // M2
81 st8.spill [r2] = r4, (GR(5) - GR(4)) // M3, bank 1
85 .mem.offset 0,0; st8.spill [r2] = r5, (GR(6) - GR(5)) // M4, bank 0
86 .mem.offset 8,0; st8.spill [r3] = r7, (BR(0) - GR(7)) // M3, bank 0
90 st8.spill [r
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/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_lower_spill.c32 * 2. The immediate offset only has 13 bits and is signed, so if we spill a lot
91 handle_oob_offset_spill(struct ir3_instruction *spill) in handle_oob_offset_spill() argument
93 unsigned components = spill->srcs[2]->uim_val; in handle_oob_offset_spill()
95 if (spill->cat6.dst_offset + components * component_bytes(spill->srcs[1]) < MAX_CAT6_SIZE) in handle_oob_offset_spill()
98 set_base_reg(spill, spill->cat6.dst_offset); in handle_oob_offset_spill()
99 reset_base_reg(spill); in handle_oob_offset_spill()
100 spill->cat6.dst_offset = 0; in handle_oob_offset_spill()
117 split_spill(struct ir3_instruction *spill) in split_spill() argument
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H A Dir3_spill.c94 * This map only contains values which we didn't spill, so it also serves as
113 /* rb tree of live intervals that we can spill, ordered by next-use distance.
115 * case. We use this list to determine what to spill.
725 spill(struct ra_spill_ctx *ctx, const struct reg_or_immed *val, in spill() function
744 struct ir3_instruction *spill = in spill() local
746 ir3_src_create(spill, INVALID_REG, ctx->base_reg->flags)->def = ctx->base_reg; in spill()
750 struct ir3_register *src = ir3_src_create(spill, INVALID_REG, src_flags); in spill()
751 ir3_src_create(spill, INVALID_REG, IR3_REG_IMMED)->uim_val = elems; in spill()
752 spill->cat6.dst_offset = spill_slot; in spill()
753 spill in spill()
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/third_party/ffmpeg/libavcodec/
H A Dxvididct.c160 int mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7, spill; in idct_col_8() local
191 LOAD_BUTTERFLY(mm0, mm1, 0 * 8, 4 * 8, spill, in); in idct_col_8()
193 BUTTERFLY(mm0, mm3, spill); in idct_col_8()
194 BUTTERFLY(mm0, mm7, spill); in idct_col_8()
212 int mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7, spill; in idct_col_4() local
237 BUTTERFLY(mm0, mm3, spill); in idct_col_4()
238 BUTTERFLY(mm0, mm7, spill); in idct_col_4()
256 int mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7, spill; in idct_col_3() local
274 BUTTERFLY(mm0, mm3, spill); in idct_col_3()
275 BUTTERFLY(mm0, mm7, spill); in idct_col_3()
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/third_party/libwebsockets/lib/misc/fts/
H A Dtrie.c170 #define spill(margin, force) \ macro
431 spill((3 * MAX_VLI) + tif->count, 0); in finalize_per_input()
452 spill(i->count, 0); in finalize_per_input()
462 spill(0, 1); in finalize_per_input()
1168 spill(15 + n, 0); in lws_fts_serialize()
1181 spill(0, 1); in lws_fts_serialize()
1201 spill(5, 0); in lws_fts_serialize()
1206 spill(0, 1); in lws_fts_serialize()
1242 spill((3 * MAX_VLI), 0); in lws_fts_serialize()
1282 spill(( in lws_fts_serialize()
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/third_party/libwebsockets/lib/roles/ws/
H A Dclient-parser-ws.c207 goto spill; in lws_ws_client_rx_sm()
229 goto spill; in lws_ws_client_rx_sm()
295 goto spill; in lws_ws_client_rx_sm()
331 goto spill; in lws_ws_client_rx_sm()
353 /* spill because we have the whole frame */ in lws_ws_client_rx_sm()
356 goto spill; in lws_ws_client_rx_sm()
371 /* spill because we filled our rx buffer */ in lws_ws_client_rx_sm()
374 spill: in lws_ws_client_rx_sm()
H A Dops-ws.c271 goto spill; in lws_ws_rx_sm()
381 goto spill; in lws_ws_rx_sm()
408 /* spill because we have the whole frame */ in lws_ws_rx_sm()
410 goto spill; in lws_ws_rx_sm()
430 /* spill because we filled our rx buffer */ in lws_ws_rx_sm()
431 spill: in lws_ws_rx_sm()
437 lwsl_parser("spill on %s\n", wsi->a.protocol->name); in lws_ws_rx_sm()
1377 * spill... they need to get the first look-in otherwise sequence will in rops_handle_POLLOUT_ws()
1380 * coming here with a NULL, zero-length ebuf means just spill pending in rops_handle_POLLOUT_ws()
1393 /* default to nobody has more to spill */ in rops_handle_POLLOUT_ws()
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/third_party/libunwind/libunwind/tests/
H A Dia64-test-nat-asm.S108 stf.spill [sp] = f2, -16
188 st8.spill [sp] = r4, -16
225 st8.spill [sp] = r6, -16;;
263 st8.spill [sp] = r6, -16;;
305 st8.spill [sp] = r6, -16;;
348 st8.spill [sp] = r6, -16;;
392 st8.spill [sp] = r7 // save r7 in the scratch stack space
/third_party/node/deps/v8/src/compiler/
H A Dc-linkage.cc159 bool spill = (i >= kParamRegisterCount); in BuildParameterLocations() local
160 if (spill) { in BuildParameterLocations()
196 bool spill = IsFloatingPoint(type.representation())
199 if (spill) {
/third_party/mesa3d/src/amd/compiler/
H A Daco_spill.cpp669 bool spill = !remat; in init_live_in_vars() local
674 spill = false; in init_live_in_vars()
679 spill = false; in init_live_in_vars()
686 spill = true; in init_live_in_vars()
689 if (spill) { in init_live_in_vars()
856 /* iterate the phi nodes for which operands to spill at the predecessor */ in add_coupling_code()
910 aco_ptr<Pseudo_instruction> spill{ in add_coupling_code()
912 spill->operands[0] = spill_op; in add_coupling_code()
913 spill->operands[1] = Operand::c32(spill_id); in add_coupling_code()
922 pred.instructions.insert(it, std::move(spill)); in add_coupling_code()
1482 spill_vgpr(spill_ctx& ctx, Block& block, std::vector<aco_ptr<Instruction>>& instructions, aco_ptr<Instruction>& spill, std::vector<uint32_t>& slots) spill_vgpr() argument
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H A Daco_interface.cpp147 aco::spill(program.get(), live_vars); in aco_postprocess_shader()
/third_party/mesa3d/src/broadcom/vulkan/
H A Dv3dv_uniforms.c651 assert(pipeline->spill.bo); in v3dv_write_uniforms_wg_offsets()
652 cl_aligned_u32(&uniforms, pipeline->spill.bo->offset); in v3dv_write_uniforms_wg_offsets()
656 assert(pipeline->spill.size_per_thread > 0); in v3dv_write_uniforms_wg_offsets()
657 cl_aligned_u32(&uniforms, pipeline->spill.size_per_thread); in v3dv_write_uniforms_wg_offsets()
688 if (pipeline->spill.bo) in v3dv_write_uniforms_wg_offsets()
689 v3dv_job_add_bo(job, pipeline->spill.bo); in v3dv_write_uniforms_wg_offsets()
H A Dv3dv_pipeline.c140 if (pipeline->spill.bo) { in v3dv_destroy_pipeline()
141 assert(pipeline->spill.size_per_thread > 0); in v3dv_destroy_pipeline()
142 v3dv_bo_free(device, pipeline->spill.bo); in v3dv_destroy_pipeline()
340 * order to get the lowest spill/fills possible, and some of them in nir_optimize()
1543 /* Checks that the pipeline has enough spill size to use for any of their
1571 if (pipeline->spill.bo) { in pipeline_check_spill_size()
1572 assert(pipeline->spill.size_per_thread > 0); in pipeline_check_spill_size()
1573 v3dv_bo_free(device, pipeline->spill.bo); in pipeline_check_spill_size()
1575 pipeline->spill.bo = in pipeline_check_spill_size()
1576 v3dv_bo_alloc(device, total_spill_size, "spill", tru in pipeline_check_spill_size()
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/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/
H A DSpiller.h21 /// Implementations are utility classes which insert spill or remat code on
29 /// spill - Spill the LRE.getParent() live interval.
30 virtual void spill(LiveRangeEdit &LRE) = 0;
35 /// Create and return a spiller that will insert spill code directly instead
H A DRegAllocBasic.cpp56 /// algorithm. It prioritizes live virtual registers by spill weight and spills
239 spiller().spill(LRE); in spillInterferences()
258 // Populate a list of physical register spill candidates. in selectOrSplit()
271 // Only virtual registers in the way, we may be able to spill them. in selectOrSplit()
281 // Try to spill another interfering reg with less spill weight. in selectOrSplit()
288 "Interference after spill."); in selectOrSplit()
293 // No other spill candidates were found, so spill the current VirtReg. in selectOrSplit()
298 spiller().spill(LR in selectOrSplit()
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H A DRegisterScavenging.cpp13 /// them to spill slots.
267 // Expire scavenge spill frameindex uses. in backward()
409 // we have to spill, and can only place the restore after From then in findSurvivorBackwards()
461 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
488 // trying to spill a smaller register, the large slot would be found
489 // first, thus making it impossible to spill the larger register later.
498 // We need to scavenge a register but have no spill slot, the target
507 // otherwise, use the emergency stack spill slot.
512 std::string Msg = std::string("Error while trying to spill ") +
514 ": Cannot scavenge register without an emergency spill slo
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H A DRegAllocFast.cpp89 bool Dirty = false; ///< Register needs spill.
224 void spill(MachineBasicBlock::iterator Before, Register VirtReg,
255 // Allocate a new stack object for this spill location... in getStackSpaceFor()
313 /// Insert spill instruction for \p AssignedReg before \p Before. Update
315 void RegAllocFast::spill(MachineBasicBlock::iterator Before, Register VirtReg, in spill() function in __anon24088::RegAllocFast
334 LLVM_DEBUG(dbgs() << "Inserting debug info due to spill:\n" << *NewDV); in spill()
423 // instruction, not on the spill. in spillVirtReg()
427 spill(MI, LR.VirtReg, LR.PhysReg, SpillKill); in spillVirtReg()
676 // Ignore the hint if we would have to spill a dirty register. in allocVirtReg()
697 // Ignore the hint if we would have to spill in allocVirtReg()
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H A DInlineSpiller.cpp76 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
77 cl::desc("Disable inline spill hoisting"));
114 /// siblings. To hoist a spill to another BB, we need to find out a live
115 /// sibling there and use it as the source of the new spill.
171 // Variables that are valid during spill(), but used by multiple methods.
177 // All registers to spill to StackSlot, including the main register.
207 void spill(LiveRangeEdit &) override;
251 // When spilling a virtual register, we also spill any snippets it is connected
257 // spill slots which can be important in tight loops.
343 LLVM_DEBUG(dbgs() << "\talso spill snippe in collectRegsToSpill()
1106 void InlineSpiller::spill(LiveRangeEdit &edit) { spill() function in InlineSpiller
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/third_party/node/deps/openssl/openssl/crypto/bn/asm/
H A Dia64-mont.pl399 stf.spill [sp]=f16,-16
401 stf.spill [r17]=f17,32
404 stf.spill [r16]=f18,32
406 stf.spill [r17]=f19,32
409 stf.spill [r16]=f20,32
411 stf.spill [r17]=f21,32
414 stf.spill [r16]=f22
416 stf.spill [r17]=f23
/third_party/openssl/crypto/bn/asm/
H A Dia64-mont.pl399 stf.spill [sp]=f16,-16
401 stf.spill [r17]=f17,32
404 stf.spill [r16]=f18,32
406 stf.spill [r17]=f19,32
409 stf.spill [r16]=f20,32
411 stf.spill [r17]=f21,32
414 stf.spill [r16]=f22
416 stf.spill [r17]=f23
/third_party/skia/third_party/externals/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DRegisterScavenging.h13 /// to spill slots.
45 /// Information on scavenged registers (held in a spill slot).
49 /// A spill slot used for scavenging a register post register allocation.
161 /// If \p AllowSpill is false, fail if a spill is required to make the
178 /// If \p AllowSpill is false, fail if a spill is required to make the
228 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
/third_party/python/Lib/
H A Dpydoc.py888 def spill(msg, attrs, predicate): function
973 attrs = spill('Methods %s' % tag, attrs,
975 attrs = spill('Class methods %s' % tag, attrs,
977 attrs = spill('Static methods %s' % tag, attrs,
1371 def spill(msg, attrs, predicate): function
1435 attrs = spill("Methods %s:\n" % tag, attrs,
1437 attrs = spill("Class methods %s:\n" % tag, attrs,
1439 attrs = spill("Static methods %s:\n" % tag, attrs,
/third_party/ffmpeg/libavcodec/x86/
H A Dh264_deblock.asm715 %define spill(x) [esp+16*x]
718 %define t4 spill(0)
719 %define t5 spill(1)
720 %define mask0 spill(2)
721 %define mask1p spill(3)
722 %define mask1q spill(4)
/third_party/mesa3d/src/nouveau/codegen/
H A Dnv50_ir_ra.cpp358 void spill(Instruction *defi, Value *slot, LValue *);
860 SpillCodeInserter& spill; member in nv50_ir::GCRA
1219 GCRA::GCRA(Function *fn, SpillCodeInserter& spill, MergedDefs& mergedDefs) : in GCRA() argument
1224 spill(spill), in GCRA()
1375 (node->degree < node->degreeLimit) ? "" : "(spill)"); in simplifyNode()
1406 ERROR("no viable spill candidates left\n"); in simplify()
1508 INFO_DBG(prog->dbgFlags, REG_ALLOC, "must spill: %%%i (size %u)\n", in selectRegisters()
1512 slot = spill.assignSlot(node->livei, lval->reg.size); in selectRegisters()
1596 "selectRegisters failed, inserting spill cod in allocateRegisters()
1716 SpillCodeInserter::spill(Instruction *defi, Value *slot, LValue *lval) spill() function in nv50_ir::SpillCodeInserter
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/third_party/node/deps/v8/src/compiler/backend/
H A Dmid-tier-register-allocator.cc265 // output to a spill slot until we enter this deferred block region. Returns
315 // Emit gap moves to / from the spill slot.
332 // Accessors for spill operand, which may still be pending allocation.
373 // Allocates pending spill operands to the |allocated| spill slot.
403 // Defines a spill range for an output operand.
411 // Defines a spill range for a Phi variable.
438 // If this spill range is only output for deferred block, then the spill in IsLiveAt()
581 // Define a spill slo in EnsureSpillRange()
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