| /third_party/vixl/src/aarch32/ |
| H A D | assembler-aarch32.h | 336 SpecialRegister spec_reg);
338 Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand);
592 SpecialFPRegister spec_reg);
594 SpecialFPRegister spec_reg,
968 SpecialRegister /*spec_reg*/) { in Delegate()
976 MaskedSpecialRegister /*spec_reg*/, in Delegate()
1762 SpecialFPRegister /*spec_reg*/) { in Delegate()
1770 SpecialFPRegister /*spec_reg*/, in Delegate()
2673 void mrs(Condition cond, Register rd, SpecialRegister spec_reg);
2674 void mrs(Register rd, SpecialRegister spec_reg) { mr argument
2679 msr(MaskedSpecialRegister spec_reg, const Operand& operand) msr() argument
4989 vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) vmrs() argument
4994 vmsr(SpecialFPRegister spec_reg, Register rt) vmsr() argument
[all...] |
| H A D | macro-assembler-aarch32.cc | 2263 MaskedSpecialRegister spec_reg, in Delegate()
2275 msr(cond, spec_reg, scratch); in Delegate()
2278 Assembler::Delegate(type, instruction, cond, spec_reg, operand); in Delegate()
2260 Delegate(InstructionType type, InstructionCondMsrOp instruction, Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand) Delegate() argument
|
| H A D | macro-assembler-aarch32.h | 1108 MaskedSpecialRegister spec_reg, in MacroAssembler()
2984 void Mrs(Condition cond, Register rd, SpecialRegister spec_reg) { in MacroAssembler() argument
2994 mrs(cond, rd, spec_reg); in MacroAssembler()
2996 void Mrs(Register rd, SpecialRegister spec_reg) { Mrs(al, rd, spec_reg); } in MacroAssembler() argument
2999 MaskedSpecialRegister spec_reg, in MacroAssembler()
3010 msr(cond, spec_reg, operand); in MacroAssembler()
3012 void Msr(MaskedSpecialRegister spec_reg, const Operand& operand) { in MacroAssembler() argument
3013 Msr(al, spec_reg, operand); in MacroAssembler()
9629 SpecialFPRegister spec_reg) { in MacroAssembler()
2998 Msr(Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand) MacroAssembler() argument
9627 Vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) MacroAssembler() argument
9641 Vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) MacroAssembler() argument
9645 Vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) MacroAssembler() argument
9657 Vmsr(SpecialFPRegister spec_reg, Register rt) MacroAssembler() argument
[all...] |
| H A D | disasm-aarch32.h | 943 void mrs(Condition cond, Register rd, SpecialRegister spec_reg);
946 MaskedSpecialRegister spec_reg,
2049 void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg);
2051 void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt);
|
| H A D | assembler-aarch32.cc | 7393 void Assembler::mrs(Condition cond, Register rd, SpecialRegister spec_reg) { in mrs() argument
7397 // MRS{<c>}{<q>} <Rd>, <spec_reg> ; T1 in mrs()
7399 EmitT32_32(0xf3ef8000U | (rd.GetCode() << 8) | (spec_reg.GetReg() << 20)); in mrs()
7404 // MRS{<c>}{<q>} <Rd>, <spec_reg> ; A1 in mrs()
7407 (spec_reg.GetReg() << 22)); in mrs()
7411 Delegate(kMrs, &Assembler::mrs, cond, rd, spec_reg); in mrs()
7415 MaskedSpecialRegister spec_reg, in msr()
7423 // MSR{<c>}{<q>} <spec_reg>, #<imm> ; A1 in msr()
7426 ((spec_reg.GetReg() & 0xf) << 16) | in msr()
7427 ((spec_reg in msr()
7414 msr(Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand) msr() argument
21252 vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) vmrs() argument
21273 vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) vmsr() argument
[all...] |
| H A D | disasm-aarch32.cc | 1949 void Disassembler::mrs(Condition cond, Register rd, SpecialRegister spec_reg) { in mrs() argument
1952 << ", " << spec_reg; in mrs() local
1956 MaskedSpecialRegister spec_reg, in msr()
1960 << spec_reg << ", " << operand; in msr()
5351 SpecialFPRegister spec_reg) { in vmrs()
5354 << ", " << spec_reg; in vmrs() local
5358 SpecialFPRegister spec_reg, in vmsr()
5362 << spec_reg << ", " << rt; in vmsr()
9487 unsigned spec_reg = ((instr >> 8) & 0xf) | in DecodeT32() local
9490 // MSR{<c>}{<q>} <spec_reg>, <R in DecodeT32()
1955 msr(Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand) msr() argument
5349 vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) vmrs() argument
5357 vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) vmsr() argument
9726 unsigned spec_reg = (instr >> 20) & 0x1; DecodeT32() local
24731 unsigned spec_reg = (instr >> 16) & 0xf; DecodeT32() local
24836 unsigned spec_reg = (instr >> 16) & 0xf; DecodeT32() local
56088 unsigned spec_reg = (instr >> 22) & 0x1; DecodeA32() local
56373 unsigned spec_reg = DecodeA32() local
61499 unsigned spec_reg = DecodeA32() local
65880 unsigned spec_reg = (instr >> 16) & 0xf; DecodeA32() local
67121 unsigned spec_reg = (instr >> 16) & 0xf; DecodeA32() local
[all...] |
| /third_party/node/deps/v8/src/diagnostics/arm/ |
| H A D | disasm-arm.cc | 616 } else { // 'spec_reg in FormatOption()
617 DCHECK(STRING_STARTS_WITH(format, "spec_reg")); in FormatOption()
900 Format(instr, "msr'cond 'spec_reg'spec_reg_fields, 'rm"); in DecodeType01()
903 Format(instr, "mrs'cond 'rd, 'spec_reg"); in DecodeType01()
|