| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1477 __ sminp(v13.V16B(), v18.V16B(), v28.V16B()); in GenerateTestSequenceNEON()
1478 __ sminp(v22.V2S(), v28.V2S(), v16.V2S()); in GenerateTestSequenceNEON()
1479 __ sminp(v15.V4H(), v12.V4H(), v5.V4H()); in GenerateTestSequenceNEON()
1480 __ sminp(v15.V4S(), v17.V4S(), v8.V4S()); in GenerateTestSequenceNEON()
1481 __ sminp(v21.V8B(), v2.V8B(), v6.V8B()); in GenerateTestSequenceNEON()
1482 __ sminp(v21.V8H(), v12.V8H(), v6.V8H()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1681 TEST_NEON(sminp_0, sminp(v0.V8B(), v1.V8B(), v2.V8B()))
1682 TEST_NEON(sminp_1, sminp(v0.V16B(), v1.V16B(), v2.V16B()))
1683 TEST_NEON(sminp_2, sminp(v0.V4H(), v1.V4H(), v2.V4H()))
1684 TEST_NEON(sminp_3, sminp(v0.V8H(), v1.V8H(), v2.V8H()))
1685 TEST_NEON(sminp_4, sminp(v0.V2S(), v1.V2S(), v2.V2S()))
1686 TEST_NEON(sminp_5, sminp(v0.V4S(), v1.V4S(), v2.V4S()))
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| H A D | test-api-movprfx-aarch64.cc | 2115 __ sminp(z27.VnB(), p3.Merging(), z27.VnB(), z1.VnB()); in TEST()
2961 __ sminp(z27.VnB(), p3.Merging(), z27.VnB(), z1.VnB()); in TEST()
3305 __ sminp(z27.VnB(), p3.Merging(), z27.VnB(), z27.VnB()); in TEST()
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| H A D | test-disasm-sve-aarch64.cc | 6862 COMPARE(sminp(z27.VnB(), p3.Merging(), z27.VnB(), z1.VnB()), in TEST()
6863 "sminp z27.b, p3/m, z27.b, z1.b"); in TEST()
6864 COMPARE(sminp(z27.VnD(), p3.Merging(), z27.VnD(), z1.VnD()), in TEST()
6865 "sminp z27.d, p3/m, z27.d, z1.d"); in TEST()
6866 COMPARE(sminp(z27.VnH(), p3.Merging(), z27.VnH(), z1.VnH()), in TEST()
6867 "sminp z27.h, p3/m, z27.h, z1.h"); in TEST()
6868 COMPARE(sminp(z27.VnS(), p3.Merging(), z27.VnS(), z1.VnS()), in TEST()
6869 "sminp z27.s, p3/m, z27.s, z1.s"); in TEST()
6903 "sminp z4.b, p1/m, z4.b, z31.b"); in TEST()
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| H A D | test-simulator-aarch64.cc | 4618 DEFINE_TEST_NEON_3SAME_NO2D(sminp, Basic)
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1218 void sminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 414 V(sminp, Sminp) \
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| H A D | assembler-arm64.cc | 3082 V(sminp, NEON_SMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
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| /third_party/vixl/src/aarch64/ |
| H A D | macro-assembler-sve-aarch64.cc | 638 V(Sminp, sminp) \
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| H A D | assembler-aarch64.h | 3070 void sminp(const VRegister& vd, const VRegister& vn, const VRegister& vm);
6253 void sminp(const ZRegister& zd,
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| H A D | simulator-aarch64.h | 3902 LogicVRegister sminp(VectorFormat vform,
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| H A D | simulator-aarch64.cc | 3467 sminp(vform, result, zdn, zm); in Simulator()
7508 sminp(vf, rd, rn, rm); in Simulator()
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| H A D | assembler-aarch64.cc | 4186 V(sminp, NEON_SMINP, vd.IsVector() && !vd.IsLaneSizeD()) \
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| H A D | assembler-sve-aarch64.cc | 7802 void Assembler::sminp(const ZRegister& zd, in sminp() function in vixl::aarch64::Assembler
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| H A D | logic-aarch64.cc | 1229 LogicVRegister Simulator::sminp(VectorFormat vform, in sminp() function in vixl::aarch64::Simulator
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| H A D | macro-assembler-aarch64.h | 2913 V(sminp, Sminp) \
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1771 LogicVRegister sminp(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4338 sminp(vf, rd, rn, rm);
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| H A D | simulator-logic-arm64.cc | 1155 LogicVRegister Simulator::sminp(VectorFormat vform, LogicVRegister dst, in sminp() function in v8::internal::Simulator
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