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Searched refs:shift_imm (Results 1 - 8 of 8) sorted by relevance

/third_party/skia/third_party/externals/swiftshader/third_party/subzero/src/DartARM32/
H A Dassembler_arm.h158 Operand(Register rm, Shift shift, uint32_t shift_imm) {
159 ASSERT(shift_imm < (1 << kShiftImmBits));
161 encoding_ = shift_imm << kShiftImmShift |
298 Address(Register rn, Register rm, Shift shift = LSL, uint32_t shift_imm = 0, in Address()
300 Operand o(rm, shift, shift_imm); in Address()
302 if ((shift == LSL) && (shift_imm == 0)) { in Address()
993 void Lsl(Register rd, Register rm, const Operand& shift_imm,
998 void Lsr(Register rd, Register rm, const Operand& shift_imm,
1003 void Asr(Register rd, Register rm, const Operand& shift_imm,
1008 void Asrs(Register rd, Register rm, const Operand &shift_imm,
[all...]
H A Dassembler_arm.cc2445 void Assembler::Lsl(Register rd, Register rm, const Operand& shift_imm,
2447 ASSERT(shift_imm.type() == 1);
2448 ASSERT(shift_imm.encoding() != 0); // Do not use Lsl if no shift is wanted.
2449 mov(rd, Operand(rm, LSL, shift_imm.encoding()), cond);
2458 void Assembler::Lsr(Register rd, Register rm, const Operand& shift_imm,
2460 ASSERT(shift_imm.type() == 1);
2461 uint32_t shift = shift_imm.encoding();
2475 void Assembler::Asr(Register rd, Register rm, const Operand& shift_imm,
2477 ASSERT(shift_imm.type() == 1);
2478 uint32_t shift = shift_imm
[all...]
/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeARM_32.c1578 if (compiler->shift_imm == 0x20) { in emit_single_op()
1582 compiler->shift_imm = (sljit_uw)(-(sljit_sw)compiler->shift_imm) & 0x1f; in emit_single_op()
1597 if (compiler->shift_imm != 0x20) { in emit_single_op()
1600 if (compiler->shift_imm != 0) in emit_single_op()
1602 RD(dst) | (compiler->shift_imm << 7) | (shift_type << 5) | RM(src2)); in emit_single_op()
2206 compiler->shift_imm = src2w & 0x1f; in sljit_emit_op2()
2209 compiler->shift_imm = 0x20; in sljit_emit_op2()
H A DsljitLir.h473 sljit_uw shift_imm; member
/third_party/node/deps/v8/src/asmjs/
H A Dasm-parser.cc1870 uint32_t shift_imm; in ShiftExpression() local
1871 if (a->IsA(AsmType::Intish()) && CheckForUnsigned(&shift_imm)) { in ShiftExpression()
1882 heap_access_shift_value_ = shift_imm; in ShiftExpression()
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.cc362 Operand::Operand(Register rm, ShiftOp shift_op, int shift_imm) { in Operand() argument
363 DCHECK(is_uint5(shift_imm)); in Operand()
368 shift_imm_ = shift_imm & 31; in Operand()
370 if ((shift_op == ROR) && (shift_imm == 0)) { in Operand()
375 // encoded as ROR with shift_imm == 0 in Operand()
376 DCHECK_EQ(shift_imm, 0); in Operand()
420 int shift_imm, AddrMode am) in MemOperand()
424 shift_imm_(shift_imm & 31), in MemOperand()
426 DCHECK(is_uint5(shift_imm)); in MemOperand()
419 MemOperand(Register rn, Register rm, ShiftOp shift_op, int shift_imm, AddrMode am) MemOperand() argument
H A Dassembler-arm.h101 // rm <shift_op> shift_imm
102 explicit Operand(Register rm, ShiftOp shift_op, int shift_imm);
204 // [rn +/- rm <shift_op> shift_imm] Offset/NegOffset
205 // [rn +/- rm <shift_op> shift_imm]! PreIndex/NegPreIndex
206 // [rn], +/- rm <shift_op> shift_imm PostIndex/NegPostIndex
207 explicit MemOperand(Register rn, Register rm, ShiftOp shift_op, int shift_imm,
/third_party/vixl/test/aarch32/
H A Dtest-assembler-aarch32.cc775 TEST(shift_imm) { in TEST()

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