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Searched refs:scvtf (Results 1 - 21 of 21) sorted by relevance

/third_party/ffmpeg/libavcodec/aarch64/
H A Dfmtconvert_neon.S28 scvtf v1.4s, v1.4s
29 scvtf v2.4s, v2.4s
37 scvtf v1.4s, v1.4s
38 scvtf v2.4s, v2.4s
52 scvtf v0.4s, v0.4s
53 scvtf v1.4s, v1.4s
55 scvtf v2.4s, v2.4s
56 scvtf v3.4s, v3.4s
70 scvtf v0.4s, v0.4s
71 scvtf v
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/third_party/vixl/test/aarch64/
H A Dtest-disasm-fp-aarch64.cc317 COMPARE(scvtf(d24, w25), "scvtf d24, w25"); in TEST()
318 COMPARE(scvtf(s24, w25), "scvtf s24, w25"); in TEST()
319 COMPARE(scvtf(d26, x0), "scvtf d26, x0"); in TEST()
320 COMPARE(scvtf(s26, x0), "scvtf s26, x0"); in TEST()
327 COMPARE(scvtf(d1, x2, 1), "scvtf d in TEST()
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H A Dtest-cpu-features-aarch64.cc681 TEST_FP(scvtf_0, scvtf(d0, w1, 5))
682 TEST_FP(scvtf_1, scvtf(d0, x1, 5))
683 TEST_FP(scvtf_2, scvtf(s0, w1, 5))
684 TEST_FP(scvtf_3, scvtf(s0, x1, 5))
685 TEST_FP(scvtf_4, scvtf(d0, w1))
686 TEST_FP(scvtf_5, scvtf(d0, x1))
687 TEST_FP(scvtf_6, scvtf(s0, w1))
688 TEST_FP(scvtf_7, scvtf(s0, x1))
3369 TEST_FP_NEON(scvtf_0, scvtf(v0.V2S(), v1.V2S(), 5))
3370 TEST_FP_NEON(scvtf_1, scvtf(v
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H A Dtest-trace-aarch64.cc592 __ scvtf(d31, d16); in GenerateTestSequenceFP()
593 __ scvtf(d26, d31, 24); in GenerateTestSequenceFP()
594 __ scvtf(d6, w16); in GenerateTestSequenceFP()
595 __ scvtf(d5, w20, 6); in GenerateTestSequenceFP()
596 __ scvtf(d16, x8); in GenerateTestSequenceFP()
597 __ scvtf(d15, x8, 10); in GenerateTestSequenceFP()
598 __ scvtf(s7, s4); in GenerateTestSequenceFP()
599 __ scvtf(s8, s15, 14); in GenerateTestSequenceFP()
600 __ scvtf(s29, w10); in GenerateTestSequenceFP()
601 __ scvtf(s1 in GenerateTestSequenceFP()
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H A Dtest-api-movprfx-aarch64.cc574 __ scvtf(z25.VnD(), p6.Merging(), z25.VnS()); in TEST()
577 __ scvtf(z0.VnD(), p3.Merging(), z0.VnD()); in TEST()
580 __ scvtf(z19.VnS(), p7.Merging(), z19.VnD()); in TEST()
583 __ scvtf(z19.VnH(), p4.Merging(), z19.VnD()); in TEST()
1055 __ scvtf(z22.VnD(), p3.Merging(), z24.VnS()); in TEST()
1058 __ scvtf(z20.VnH(), p2.Merging(), z9.VnH()); in TEST()
1061 __ scvtf(z19.VnS(), p1.Merging(), z6.VnD()); in TEST()
1064 __ scvtf(z31.VnH(), p3.Merging(), z22.VnD()); in TEST()
1924 __ scvtf(z2.VnD(), p1.Merging(), z16.VnS()); in TEST()
1927 __ scvtf(z1 in TEST()
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H A Dtest-simulator-aarch64.cc4784 DEFINE_TEST_NEON_2OPIMM_HSD(scvtf,
4816 DEFINE_TEST_NEON_2OPIMM_SCALAR_HSD(scvtf,
H A Dtest-disasm-sve-aarch64.cc1851 COMPARE(scvtf(z16.VnH(), p6.Merging(), z5.VnH()), "scvtf z16.h, p6/m, z5.h"); in TEST()
1852 COMPARE(scvtf(z31.VnD(), p5.Merging(), z26.VnS()), in TEST()
1853 "scvtf z31.d, p5/m, z26.s"); in TEST()
1854 COMPARE(scvtf(z0.VnH(), p7.Merging(), z0.VnS()), "scvtf z0.h, p7/m, z0.s"); in TEST()
1855 COMPARE(scvtf(z12.VnS(), p7.Merging(), z0.VnS()), "scvtf z12.s, p7/m, z0.s"); in TEST()
1856 COMPARE(scvtf(z17.VnD(), p1.Merging(), z17.VnD()), in TEST()
1857 "scvtf z1 in TEST()
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/third_party/node/deps/v8/src/codegen/arm64/
H A Dassembler-arm64.h1790 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0);
1796 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
H A Dmacro-assembler-arm64-inl.h914 scvtf(fd, rn, fbits); in Scvtf()
H A Dmacro-assembler-arm64.h1135 scvtf(vd, vn, fbits); in Scvtf()
H A Dassembler-arm64.cc2816 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf() function in v8::internal::Assembler
2836 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf() function in v8::internal::Assembler
/third_party/node/deps/v8/src/execution/arm64/
H A Dsimulator-arm64.cc4106 scvtf(fpf, rd, rn, 0, fpcr_rounding);
5416 scvtf(fpf, rd, rn, 0, fpcr_rounding);
5804 scvtf(vf, rd, rn, right_shift, fpcr_rounding);
5885 scvtf(vf, rd, rn, right_shift, fpcr_rounding);
H A Dsimulator-arm64.h1891 LogicVRegister scvtf(VectorFormat vform, LogicVRegister dst,
H A Dsimulator-logic-arm64.cc4195 LogicVRegister Simulator::scvtf(VectorFormat vform, LogicVRegister dst, in scvtf() function in v8::internal::Simulator
/third_party/vixl/src/aarch64/
H A Dsimulator-aarch64.cc7154 scvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
7236 scvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
8825 scvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
8918 scvtf(fpf, rd, rn, 0, fpcr_rounding); in Simulator()
9387 scvtf(vf, rd, rn, right_shift, fpcr_rounding); in Simulator()
9472 scvtf(vf, rd, rn, right_shift, fpcr_rounding); in Simulator()
10905 scvtf(vform, dst_data_size, src_data_size, zd, pg, zn, fpcr_rounding); in Simulator()
H A Dsimulator-aarch64.h4132 LogicVRegister scvtf(VectorFormat vform,
4140 LogicVRegister scvtf(VectorFormat vform,
H A Dassembler-aarch64.h2476 void scvtf(const VRegister& fd, const Register& rn, int fbits = 0);
2482 void scvtf(const VRegister& fd, const VRegister& vn, int fbits = 0);
5272 void scvtf(const ZRegister& zd, const PRegisterM& pg, const ZRegister& zn);
H A Dlogic-aarch64.cc6844 LogicVRegister Simulator::scvtf(VectorFormat vform,
6888 LogicVRegister Simulator::scvtf(VectorFormat vform,
6893 return scvtf(vform,
H A Dmacro-assembler-aarch64.h2435 scvtf(vd, rn, fbits); in Scvtf()
3499 scvtf(vd, vn, fbits); in Scvtf()
5803 scvtf(zd, pg, zn); in Scvtf()
H A Dassembler-aarch64.cc3785 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) {
3804 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) {
H A Dassembler-sve-aarch64.cc1904 void Assembler::scvtf(const ZRegister& zd, in scvtf() function in vixl::aarch64::Assembler

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