| /third_party/ffmpeg/libavcodec/aarch64/ |
| H A D | h264pred_neon.S | 134 saddw v2.4s, v3.4s, v2.4h
495 saddw v2.4s, v3.4s, v2.4h
516 saddw v16.4s, v16.4s, v0.4h
518 saddw v3.4s, v3.4s, v2.4h
525 saddw v16.4s, v16.4s, v2.4h
526 saddw v17.4s, v17.4s, v2.4h
602 saddw v1.4s, v1.4s, v0.4h
610 saddw v1.4s, v1.4s, v3.4h
611 saddw v2.4s, v2.4s, v3.4h
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| H A D | h264dsp_neon.S | 101 saddw v28.8H, v28.8H, v4.8B
406 saddw v28.8H, v28.8H, v4.8B
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| H A D | vp8dsp_neon.S | 350 saddw v18.8h, v18.8h, v20.8b // w += clamp(PS1-QS1)
430 saddw v22.8h, v22.8h, v18.8b
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| H A D | vp9lpf_neon.S | 111 saddw \dst1, \in1, \in3\().8b
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| /third_party/node/deps/v8/src/codegen/arm64/ |
| H A D | assembler-arm64.h | 1282 void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | macro-assembler-arm64.h | 409 V(saddw, Saddw) \
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| H A D | assembler-arm64.cc | 1831 void Assembler::saddw(const VRegister& vd, const VRegister& vn, in saddw() function in v8::internal::Assembler
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| /third_party/vixl/test/aarch64/ |
| H A D | test-trace-aarch64.cc | 1408 __ saddw(v24.V2D(), v11.V2D(), v18.V2S()); in GenerateTestSequenceNEON()
1409 __ saddw(v13.V4S(), v12.V4S(), v6.V4H()); in GenerateTestSequenceNEON()
1410 __ saddw(v19.V8H(), v19.V8H(), v7.V8B()); in GenerateTestSequenceNEON()
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| H A D | test-cpu-features-aarch64.cc | 1618 TEST_NEON(saddw_0, saddw(v0.V8H(), v1.V8H(), v2.V8B()))
1619 TEST_NEON(saddw_1, saddw(v0.V4S(), v1.V4S(), v2.V4H()))
1620 TEST_NEON(saddw_2, saddw(v0.V2D(), v1.V2D(), v2.V2S()))
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| H A D | test-simulator-aarch64.cc | 4728 DEFINE_TEST_NEON_3DIFF_WIDE(saddw, Basic)
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| /third_party/node/deps/v8/src/execution/arm64/ |
| H A D | simulator-arm64.h | 1837 LogicVRegister saddw(VectorFormat vform, LogicVRegister dst,
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| H A D | simulator-arm64.cc | 4558 saddw(vf_l, rd, rn, rm);
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| H A D | simulator-logic-arm64.cc | 2379 LogicVRegister Simulator::saddw(VectorFormat vform, LogicVRegister dst, in saddw() function in v8::internal::Simulator
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| /third_party/vixl/src/aarch64/ |
| H A D | simulator-aarch64.cc | 2583 saddw(vform, zd, zn, zm_b); in Simulator()
2586 saddw(vform, zd, zn, zm_t); in Simulator()
7822 saddw(vf_l, rd, rn, rm); in Simulator()
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| H A D | simulator-aarch64.h | 4027 LogicVRegister saddw(VectorFormat vform,
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| H A D | assembler-aarch64.h | 3153 void saddw(const VRegister& vd, const VRegister& vn, const VRegister& vm);
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| H A D | assembler-aarch64.cc | 3054 void Assembler::saddw(const VRegister& vd,
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| H A D | logic-aarch64.cc | 3550 LogicVRegister Simulator::saddw(VectorFormat vform,
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| H A D | macro-assembler-aarch64.h | 2906 V(saddw, Saddw) \
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