| /third_party/mesa3d/src/gallium/drivers/r600/sfn/ |
| H A D | sfn_nir_lower_tess_io.cpp | 110 r600_tcs_base_address(nir_builder *b, nir_ssa_def *param_base, nir_ssa_def *rel_patch_id) in r600_tcs_base_address() argument
113 rel_patch_id, in r600_tcs_base_address()
345 auto rel_patch_id = r600_load_rel_patch_id(b); in r600_lower_tess_io_impl() local
366 emil_lsd_in_addr(b, load_in_param_base, rel_patch_id, op) : in r600_lower_tess_io_impl()
367 emil_lsd_out_addr(b, load_in_param_base, rel_patch_id, op, nir_var_shader_in, 0); in r600_lower_tess_io_impl()
372 nir_ssa_def *addr = emil_lsd_out_addr(b, load_out_param_base, rel_patch_id, op, nir_var_shader_out, 1); in r600_lower_tess_io_impl()
378 nir_ssa_def *addr = emil_lsd_out_addr(b, load_out_param_base, rel_patch_id, op, nir_var_shader_out, 0); in r600_lower_tess_io_impl()
384 r600_tcs_base_address(b, load_out_param_base, rel_patch_id): in r600_lower_tess_io_impl()
387 rel_patch_id, NULL, NULL); in r600_lower_tess_io_impl()
394 nir_ssa_def *addr = r600_tcs_base_address(b, load_out_param_base, rel_patch_id); in r600_lower_tess_io_impl()
415 auto rel_patch_id = r600_load_rel_patch_id(b); r600_lower_tess_io_impl() local
507 auto rel_patch_id = r600_load_rel_patch_id(b); r600_append_tcs_TF_emission() local
[all...] |
| /third_party/mesa3d/src/gallium/drivers/radeonsi/ |
| H A D | si_shader_llvm_tess.c | 91 LLVMValueRef rel_patch_id = si_get_rel_patch_id(ctx); in get_tcs_out_current_patch_data_offset() local
93 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id, patch0_patch_data_offset); in get_tcs_out_current_patch_data_offset()
151 LLVMValueRef rel_patch_id, LLVMValueRef vertex_index, in get_tcs_tes_buffer_address()
164 base_addr = ac_build_imad(&ctx->ac, rel_patch_id, vertices_per_patch, vertex_index); in get_tcs_tes_buffer_address()
167 base_addr = rel_patch_id; in get_tcs_tes_buffer_address()
284 LLVMValueRef rel_patch_id, LLVMValueRef invocation_id, in si_write_tess_factors()
387 LLVMBuildMul(ctx->ac.builder, rel_patch_id, LLVMConstInt(ctx->ac.i32, 4 * stride, 0), ""); in si_write_tess_factors()
393 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, rel_patch_id, ctx->ac.i32_0, ""), 6504); in si_write_tess_factors()
422 tf_outer_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NULL, in si_write_tess_factors()
431 tf_inner_offset = get_tcs_tes_buffer_address(ctx, rel_patch_id, NUL in si_write_tess_factors()
150 get_tcs_tes_buffer_address(struct si_shader_context *ctx, LLVMValueRef rel_patch_id, LLVMValueRef vertex_index, LLVMValueRef param_index) get_tcs_tes_buffer_address() argument
283 si_write_tess_factors(struct si_shader_context *ctx, union si_shader_part_key *key, LLVMValueRef rel_patch_id, LLVMValueRef invocation_id, LLVMValueRef tcs_out_current_patch_data_offset, LLVMValueRef invoc0_tf_outer[4], LLVMValueRef invoc0_tf_inner[2]) si_write_tess_factors() argument
447 LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset; si_llvm_tcs_build_end() local
642 struct ac_arg rel_patch_id; /* patch index within the wave (REL_PATCH_ID) */ si_llvm_build_tcs_epilog() local
[all...] |
| /third_party/mesa3d/src/amd/common/ |
| H A D | ac_nir_lower_tess_io_to_mem.c | 79 * TCS per-vertex inputs for patch 2 <─── hs_per_vertex_input_lds_offset (rel_patch_id = 2)
85 * TCS per-vertex outputs for patch 2 <─── hs_output_lds_offset (rel_patch_id = 2, per-vertex)
86 * TCS per-patch outputs for patch 2 <─── hs_output_lds_offset (rel_patch_id = 2, per-patch)
99 * attr 0 of patch 1 vertex 2 <─── hs_per_vertex_output_vmem_offset (attribute slot = 0, rel_patch_id = 1, vertex index = 1)
112 * per-patch attr 0 of patch 2 <─── hs_per_patch_output_vmem_offset (attribute slot = 0, rel_patch_id = 2)
306 nir_ssa_def *rel_patch_id = nir_load_tess_rel_patch_id_amd(b); in hs_per_vertex_input_lds_offset() local
313 nir_ssa_def *tcs_in_current_patch_offset = nir_imul(b, rel_patch_id, tcs_in_patch_stride); in hs_per_vertex_input_lds_offset()
337 nir_ssa_def *rel_patch_id = nir_load_tess_rel_patch_id_amd(b); in hs_output_lds_offset() local
338 nir_ssa_def *patch_offset = nir_imul_imm(b, rel_patch_id, output_patch_stride); in hs_output_lds_offset()
377 nir_ssa_def *rel_patch_id in hs_per_vertex_output_vmem_offset() local
402 nir_ssa_def *rel_patch_id = nir_load_tess_rel_patch_id_amd(b); hs_per_patch_output_vmem_offset() local
581 nir_ssa_def *rel_patch_id = nir_load_tess_rel_patch_id_amd(b); hs_emit_write_tess_factors() local
[all...] |
| /third_party/mesa3d/src/freedreno/ir3/ |
| H A D | ir3_context.h | 100 struct ir3_instruction *rel_patch_id; member
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| H A D | ir3_compiler_nir.c | 2119 dst[0] = ctx->rel_patch_id; in emit_intrinsic()
4346 ctx->rel_patch_id = in emit_instructions()
4360 ctx->rel_patch_id = in emit_instructions()
4370 ctx->rel_patch_id = in emit_instructions()
4657 if (so->type == MESA_SHADER_VERTEX && ctx->rel_patch_id) in ir3_compile_shader_nir()
4664 if (so->type == MESA_SHADER_VERTEX && ctx->rel_patch_id) { in ir3_compile_shader_nir()
4667 struct ir3_instruction *out = ir3_collect(ctx->block, ctx->rel_patch_id); in ir3_compile_shader_nir()
4868 ctx->rel_patch_id->dsts[0]->num = regid(0, 1); in ir3_compile_shader_nir()
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