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Searched refs:reg_type (Results 1 - 21 of 21) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
H A Dbrw_reg_type.c92 enum hw_reg_type reg_type; member
239 enum hw_3src_reg_type reg_type; member
356 assert(table[type].reg_type != (enum hw_reg_type)INVALID); in brw_reg_type_to_hw_type()
357 return table[type].reg_type; in brw_reg_type_to_hw_type()
396 if (table[i].reg_type == (enum hw_reg_type)hw_type) { in brw_hw_type_to_reg_type()
425 assert(table[type].reg_type != (enum hw_3src_reg_type)INVALID); in brw_reg_type_to_a16_hw_3src_type()
426 return table[type].reg_type; in brw_reg_type_to_a16_hw_3src_type()
439 return gfx125_hw_3src_type[type].reg_type; in brw_reg_type_to_a1_hw_3src_type()
442 return gfx12_hw_3src_type[type].reg_type; in brw_reg_type_to_a1_hw_3src_type()
445 return gfx11_hw_3src_type[type].reg_type; in brw_reg_type_to_a1_hw_3src_type()
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H A Dbrw_fs_nir.cpp322 const brw_reg_type reg_type = reg->bit_size == 8 ? BRW_REGISTER_TYPE_B : in nir_emit_impl() local
324 nir_locals[reg->index] = bld.vgrf(reg_type, size); in nir_emit_impl()
2026 const brw_reg_type reg_type =
2028 fs_reg reg = bld.vgrf(reg_type, instr->def.num_components);
2073 const brw_reg_type reg_type =
2075 reg = bld.vgrf(reg_type, src.ssa->num_components);
2122 const brw_reg_type reg_type =
2128 bld.vgrf(reg_type, dest.ssa.num_components);
/third_party/cups-filters/cupsfilters/
H A Dipp.c488 *reg_type, in ippfind_based_uri_converter() local
513 if ((reg_type = strstr(hostname, "._tcp")) == NULL) { in ippfind_based_uri_converter()
524 reg_type --; in ippfind_based_uri_converter()
525 while (reg_type >= hostname && *reg_type != '.') in ippfind_based_uri_converter()
526 reg_type --; in ippfind_based_uri_converter()
527 if (reg_type < hostname) { in ippfind_based_uri_converter()
531 *reg_type++ = '\0'; in ippfind_based_uri_converter()
535 ippfind_argv[i++] = reg_type; /* list IPP(S) entries */ in ippfind_based_uri_converter()
636 ptr = strchr(reg_type, ' in ippfind_based_uri_converter()
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/third_party/skia/third_party/externals/spirv-tools/source/opt/
H A Dir_context.cpp799 analysis::Type* reg_type; in GetBuiltinInputVarId() local
805 reg_type = type_mgr->GetRegisteredType(&v4float_ty); in GetBuiltinInputVarId()
814 reg_type = type_mgr->GetRegisteredType(&uint_ty); in GetBuiltinInputVarId()
822 reg_type = type_mgr->GetRegisteredType(&v3uint_ty); in GetBuiltinInputVarId()
829 reg_type = type_mgr->GetRegisteredType(&v3float_ty); in GetBuiltinInputVarId()
836 reg_type = type_mgr->GetRegisteredType(&v4uint_ty); in GetBuiltinInputVarId()
844 uint32_t type_id = type_mgr->GetTypeInstruction(reg_type); in GetBuiltinInputVarId()
/third_party/skia/third_party/externals/swiftshader/third_party/SPIRV-Tools/source/opt/
H A Dir_context.cpp799 analysis::Type* reg_type; in GetBuiltinInputVarId() local
805 reg_type = type_mgr->GetRegisteredType(&v4float_ty); in GetBuiltinInputVarId()
814 reg_type = type_mgr->GetRegisteredType(&uint_ty); in GetBuiltinInputVarId()
822 reg_type = type_mgr->GetRegisteredType(&v3uint_ty); in GetBuiltinInputVarId()
829 reg_type = type_mgr->GetRegisteredType(&v3float_ty); in GetBuiltinInputVarId()
836 reg_type = type_mgr->GetRegisteredType(&v4uint_ty); in GetBuiltinInputVarId()
844 uint32_t type_id = type_mgr->GetTypeInstruction(reg_type); in GetBuiltinInputVarId()
/third_party/mesa3d/src/intel/tools/
H A Di965_gram.y351 enum brw_reg_type reg_type;
524 %type <reg_type> reg_type imm_type
1515 dstreg dstregion writemask reg_type
1529 dstoperandex_typed dstregion writemask reg_type
1541 | nullreg dstregion writemask reg_type
1648 directgenreg region reg_type
1677 | accreg region reg_type
1687 srcarcoperandex_typed region reg_type
1701 | nullreg region reg_type
2099 reg_type: global() label
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/third_party/cups-filters/utils/
H A Ddriverless.c75 *reg_type = NULL, in listPrintersInArray() local
97 reg_type = "_ipp._tcp"; in listPrintersInArray()
100 reg_type = "_ipps._tcp"; in listPrintersInArray()
155 service_name, reg_type, domain); in listPrintersInArray()
684 reg_type_no = 1, /* reg_type 0 for only IPP in main()
/third_party/spirv-tools/source/opt/
H A Dir_context.cpp860 analysis::Type* reg_type; in GetBuiltinInputVarId() local
866 reg_type = type_mgr->GetRegisteredType(&v4float_ty); in GetBuiltinInputVarId()
875 reg_type = type_mgr->GetRegisteredType(&uint_ty); in GetBuiltinInputVarId()
883 reg_type = type_mgr->GetRegisteredType(&v3uint_ty); in GetBuiltinInputVarId()
890 reg_type = type_mgr->GetRegisteredType(&v3float_ty); in GetBuiltinInputVarId()
897 reg_type = type_mgr->GetRegisteredType(&v4uint_ty); in GetBuiltinInputVarId()
905 uint32_t type_id = type_mgr->GetTypeInstruction(reg_type); in GetBuiltinInputVarId()
/third_party/mesa3d/src/gallium/auxiliary/gallivm/
H A Dlp_bld_ir_common.c279 LLVMTypeRef reg_type = LLVMIntTypeInContext(gallivm->context, in lp_exec_endloop() local
320 LLVMBuildBitCast(builder, mask->exec_mask, reg_type, ""), in lp_exec_endloop()
321 LLVMConstNull(reg_type), "i1cond"); in lp_exec_endloop()
H A Dlp_bld_flow.c146 LLVMBuildBitCast(builder, value, mask->reg_type, ""), in lp_build_mask_check()
147 LLVMConstNull(mask->reg_type), in lp_build_mask_check()
170 mask->reg_type = LLVMIntTypeInContext(gallivm->context, type.width * type.length); in lp_build_mask_begin()
H A Dlp_bld_flow.h75 LLVMTypeRef reg_type; member
/third_party/mesa3d/src/freedreno/ir3/
H A Dir3_shader.c691 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r"; in dump_reg() local
692 fprintf(out, "; %s: %s%d.%c\n", name, reg_type, (r & ~HALF_REG_ID) >> 2, in dump_reg()
833 const char *reg_type = so->outputs[i].half ? "hr" : "r"; in ir3_shader_disasm() local
834 fprintf(out, " %s%d.%c (%s)", reg_type, (regid >> 2), "xyzw"[regid & 0x3], in ir3_shader_disasm()
/third_party/node/deps/v8/src/codegen/arm/
H A Dassembler-arm.cc3000 // Split five bit reg_code based on size of reg_type.
3004 static void SplitRegCode(VFPType reg_type, int reg_code, int* vm, int* m) { in SplitRegCode() argument
3006 if (IsIntegerVFPType(reg_type) || !IsDoubleVFPType(reg_type)) { in SplitRegCode()
3958 static Instr EncodeNeonDupOp(NeonSize size, NeonRegType reg_type, int dst_code, in EncodeNeonDupOp() argument
3967 NeonSplitCode(reg_type, dst_code, &vd, &d, &qbit); in EncodeNeonDupOp()
4071 static Instr EncodeNeonUnaryOp(UnaryOp op, NeonRegType reg_type, NeonSize size, in EncodeNeonUnaryOp() argument
4160 NeonSplitCode(reg_type, dst_code, &vd, &d, &op_encoding); in EncodeNeonUnaryOp()
4162 NeonSplitCode(reg_type, src_code, &vm, &m, &op_encoding); in EncodeNeonUnaryOp()
4220 static Instr EncodeNeonBinaryBitwiseOp(BinaryBitwiseOp op, NeonRegType reg_type, in EncodeNeonBinaryBitwiseOp() argument
4602 EncodeNeonShiftRegisterOp(NeonShiftOp op, NeonDataType dt, NeonRegType reg_type, int dst_code, int src_code, int shift_code) EncodeNeonShiftRegisterOp() argument
4620 EncodeNeonShiftOp(NeonShiftOp op, NeonSize size, bool is_unsigned, NeonRegType reg_type, int dst_code, int src_code, int shift) EncodeNeonShiftOp() argument
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/third_party/protobuf/src/google/protobuf/
H A Drepeated_field.h136 #define PROTO_MEMSWAP_DEF_SIZE(reg_type, max_size) \
138 typename std::enable_if<(kSize >= sizeof(reg_type) && kSize < (max_size)), \
141 SwapBlock<reg_type>(p, q); \
142 memswap<kSize - sizeof(reg_type)>(p + sizeof(reg_type), \
143 q + sizeof(reg_type)); \
/third_party/mesa3d/src/gallium/drivers/etnaviv/
H A Detnaviv_compiler_nir.h257 enum reg_type { enum
/third_party/vixl/src/aarch64/
H A Ddisasm-aarch64.cc6457 CPURegister::RegisterType reg_type = CPURegister::kRegister; in Disassembler() local
6475 reg_type = CPURegister::kRegister; in Disassembler()
6479 reg_type = CPURegister::kRegister; in Disassembler()
6483 reg_type = CPURegister::kVRegister; in Disassembler()
6487 reg_type = CPURegister::kVRegister; in Disassembler()
6491 reg_type = CPURegister::kVRegister; in Disassembler()
6495 reg_type = CPURegister::kVRegister; in Disassembler()
6499 reg_type = CPURegister::kVRegister; in Disassembler()
6504 reg_type = CPURegister::kVRegister; in Disassembler()
6518 AppendRegisterNameToOutput(instr, CPURegister(reg_num, reg_size, reg_type)); in Disassembler()
7232 char reg_type = ((ext == UXTW) || (ext == SXTW)) ? 'w' : 'x'; Disassembler() local
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/third_party/wpa_supplicant/wpa_supplicant-2.9/src/drivers/
H A Ddriver.h94 * enum reg_type - Regulatory change types
96 enum reg_type { enum
5562 enum reg_type type;
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/src/drivers/
H A Ddriver.h94 * enum reg_type - Regulatory change types
96 enum reg_type { enum
6100 enum reg_type type;
/third_party/mesa3d/src/amd/compiler/
H A Daco_instruction_selection.cpp4182 RegType reg_type = RegType::sgpr;
4185 reg_type = RegType::vgpr;
4194 tmp[0] = bld.tmp(RegClass::get(reg_type, tmp_size));
4203 RegClass::get(reg_type, tmp[0].bytes() / component_size * component_size);
4208 RegClass elem_rc = RegClass::get(reg_type, component_size);
5012 create_vec_from_array(isel_context* ctx, Temp arr[], unsigned cnt, RegType reg_type,
5019 dst = bld.tmp(RegClass(reg_type, cnt * dword_size));
5032 Temp zero = bld.copy(bld.def(RegClass(reg_type, dword_size)),
/third_party/wpa_supplicant/wpa_supplicant-2.9/wpa_supplicant/
H A Devents.c3696 static const char * reg_type_str(enum reg_type type) in reg_type_str()
/third_party/wpa_supplicant/wpa_supplicant-2.9_standard/wpa_supplicant/
H A Devents.c5181 static const char * reg_type_str(enum reg_type type)

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