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Searched refs:reg_mode (Results 1 - 6 of 6) sorted by relevance

/third_party/mesa3d/src/panfrost/midgard/
H A Dmidgard_print_constant.c34 midgard_reg_mode reg_mode, bool half, in mir_print_constant_component()
64 reg_mode--; in mir_print_constant_component()
66 switch (reg_mode) { in mir_print_constant_component()
33 mir_print_constant_component(FILE *fp, const midgard_constants *consts, unsigned c, midgard_reg_mode reg_mode, bool half, unsigned mod, midgard_alu_op op) mir_print_constant_component() argument
H A Ddisassemble.c129 midgard_reg_mode reg_mode) in validate_expand_mode()
136 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
137 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
141 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
142 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
146 assert(reg_mode == midgard_reg_mode_8 || in validate_expand_mode()
147 reg_mode == midgard_reg_mode_16); in validate_expand_mode()
151 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
155 assert(reg_mode != midgard_reg_mode_8); in validate_expand_mode()
159 assert(reg_mode in validate_expand_mode()
128 validate_expand_mode(midgard_src_expand_mode expand_mode, midgard_reg_mode reg_mode) validate_expand_mode() argument
382 print_vec_selectors_64(FILE *fp, unsigned swizzle, midgard_reg_mode reg_mode, midgard_src_expand_mode expand_mode, unsigned selector_offset, uint8_t mask) print_vec_selectors_64() argument
417 print_vec_selectors(FILE *fp, unsigned swizzle, midgard_reg_mode reg_mode, unsigned selector_offset, uint8_t mask, unsigned *mask_offset) print_vec_selectors() argument
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H A Dmidgard_emit.c234 midgard_reg_mode reg_mode = reg_mode_for_bitsize(base_size); in mir_pack_swizzle() local
236 if (reg_mode == midgard_reg_mode_64) { in mir_pack_swizzle()
303 if (reg_mode == midgard_reg_mode_16 && sz == 16) { in mir_pack_swizzle()
306 } else if (reg_mode == midgard_reg_mode_16 && sz == 8) { in mir_pack_swizzle()
313 } else if (reg_mode == midgard_reg_mode_32 && sz == 16) { in mir_pack_swizzle()
316 } else if (reg_mode == midgard_reg_mode_8) { in mir_pack_swizzle()
675 .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)) in vector_alu_from_instr()
H A Dmidgard_print.c127 midgard_reg_mode reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)); in mir_print_embedded_constant() local
148 swizzle[comp], reg_mode, in mir_print_embedded_constant()
H A Dhelpers.h435 unsigned c, midgard_reg_mode reg_mode, bool half,
H A Dmidgard.h315 midgard_reg_mode reg_mode : 2; member

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