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Searched refs:reg_map (Results 1 - 16 of 16) sorted by relevance

/third_party/pcre2/pcre2/src/sljit/
H A DsljitNativeX86_64.c40 *inst++ = REX_W | ((reg_map[reg] <= 7) ? 0 : REX_B); in emit_load_imm64()
41 *inst++ = U8(MOV_r_i32 | (reg_map[reg] & 0x7)); in emit_load_imm64()
131 if (reg_map[b & REG_MASK] >= 8) in emit_x86_instruction()
139 if (reg_map[OFFS_REG(b)] >= 8) in emit_x86_instruction()
145 if (reg_map[b] >= 8) in emit_x86_instruction()
174 /* reg_map[SLJIT_PREF_SHIFT_REG] is less than 8. */ in emit_x86_instruction()
176 if (reg_map[a] >= 8) in emit_x86_instruction()
295 SLJIT_ASSERT(reg_map[TMP_REG2] >= 8); in generate_far_jump_code()
405 size = reg_map[i] >= 8 ? 2 : 1; in sljit_emit_enter()
409 if (reg_map[ in sljit_emit_enter()
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H A DsljitNativeX86_32.c91 else if (reg_map[b & REG_MASK] == 5) { in emit_x86_instruction()
93 if ((b & OFFS_REG_MASK) && (immb & 0x3) == 0 && reg_map[OFFS_REG(b)] != 5) in emit_x86_instruction()
99 if (reg_map[b & REG_MASK] == 4 && !(b & OFFS_REG_MASK)) in emit_x86_instruction()
154 *buf_ptr = U8(reg_map[a] << 3); in emit_x86_instruction()
170 *buf_ptr = U8(*buf_ptr | MOD_REG | (!(flags & EX86_SSE2_OP2) ? reg_map[b] : b)); in emit_x86_instruction()
173 reg_map_b = reg_map[b & REG_MASK]; in emit_x86_instruction()
187 *buf_ptr++ = U8(reg_map_b | (reg_map[OFFS_REG(b)] << 3)); in emit_x86_instruction()
204 *buf_ptr++ = U8(reg_map_b | (reg_map[OFFS_REG(b)] << 3) | (immb << 6)); in emit_x86_instruction()
355 PUSH_REG(reg_map[TMP_REG1]); in sljit_emit_enter()
358 PUSH_REG(reg_map[SLJIT_S in sljit_emit_enter()
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H A DsljitNativeX86_common.c71 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 3] = { variable
93 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
96 /* low-map. reg_map & 0x7. */
102 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
105 /* low-map. reg_map & 0x7. */
901 *inst++ = REX_W | (reg_map[reg] <= 7 ? 0 : REX_B); in emit_rdssp()
905 *inst = (0x3 << 6) | (0x1 << 3) | (reg_map[reg] & 0x7); in emit_rdssp()
925 *inst++ = REX_W | (reg_map[reg] <= 7 ? 0 : REX_B); in emit_incssp()
929 *inst = (0x3 << 6) | (0x5 << 3) | (reg_map[reg] & 0x7); in emit_incssp()
958 SLJIT_ASSERT(reg_map[TMP_REG in adjust_shadow_stack()
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H A DsljitNativeARM_T2_32.c48 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
62 #define RD3(rd) ((sljit_ins)reg_map[rd])
63 #define RN3(rn) ((sljit_ins)reg_map[rn] << 3)
64 #define RM3(rm) ((sljit_ins)reg_map[rm] << 6)
65 #define RDN3(rdn) ((sljit_ins)reg_map[rdn] << 8)
71 (((sljit_ins)reg_map[rn] << 3) | ((sljit_ins)reg_map[rd] & 0x7) | (((sljit_ins)reg_map[rd] & 0x8) << 4))
73 (reg_map[reg1] <= 7 && reg_map[reg
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H A DsljitNativeARM_32.c63 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
71 #define RM(rm) ((sljit_uw)reg_map[rm])
72 #define RM8(rm) ((sljit_uw)reg_map[rm] << 8)
73 #define RD(rd) ((sljit_uw)reg_map[rd] << 12)
74 #define RN(rn) ((sljit_uw)reg_map[rn] << 16)
286 SLJIT_ASSERT(reg_map[TMP_REG1] != 14); in emit_blx()
1082 imm |= (sljit_uw)1 << reg_map[i]; in sljit_emit_enter()
1085 imm |= (sljit_uw)1 << reg_map[i]; in sljit_emit_enter()
1087 SLJIT_ASSERT(reg_map[TMP_REG2] == 14); in sljit_emit_enter()
1266 SLJIT_ASSERT(reg_map[TMP_REG in emit_stack_frame_release()
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H A DsljitNativeARM_64.c46 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 8] = { variable
55 #define RD(rd) ((sljit_ins)reg_map[rd])
56 #define RT(rt) ((sljit_ins)reg_map[rt])
57 #define RN(rn) ((sljit_ins)reg_map[rn] << 5)
58 #define RT2(rt2) ((sljit_ins)reg_map[rt2] << 10)
59 #define RM(rm) ((sljit_ins)reg_map[rm] << 16)
1577 SLJIT_ASSERT(reg_map[1] == 0 && reg_map[3] == 2 && reg_map[5] == 4); in sljit_emit_op_src()
1579 /* The reg_map[o in sljit_emit_op_src()
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H A DsljitNativePPC_common.c107 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 7] = { variable
118 #define D(d) ((sljit_ins)reg_map[d] << 21)
119 #define S(s) ((sljit_ins)reg_map[s] << 21)
120 #define A(a) ((sljit_ins)reg_map[a] << 16)
121 #define B(b) ((sljit_ins)reg_map[b] << 11)
122 #define C(c) ((sljit_ins)reg_map[c] << 6)
1860 return reg_map[reg]; in sljit_get_register_index()
H A DsljitNativeMIPS_32.c78 SLJIT_ASSERT(reg_map[TMP_REG1] == 4 && freg_map[TMP_FREG1] == 12); in call_with_args()
H A DsljitNativeMIPS_64.c160 SLJIT_ASSERT(reg_map[TMP_REG1] == 4 && freg_map[TMP_FREG1] == 12); in call_with_args()
H A DsljitNativeMIPS_common.c90 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 5] = { variable
112 #define S(s) ((sljit_ins)reg_map[s] << 21)
113 #define T(t) ((sljit_ins)reg_map[t] << 16)
114 #define D(d) ((sljit_ins)reg_map[d] << 11)
125 #define DR(dr) (reg_map[dr])
2524 return reg_map[reg]; in sljit_get_register_index()
H A DsljitNativeS390X.c50 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 4] = { variable
68 * that should be used instead of the usual index into reg_map[] and
72 static const sljit_gpr r0 = 0; /* reg_map[SLJIT_NUMBER_OF_REGISTERS + 2]: 0 in address calculations; reserved */
73 static const sljit_gpr r1 = 1; /* reg_map[SLJIT_NUMBER_OF_REGISTERS + 3]: reserved */
74 static const sljit_gpr r2 = 2; /* reg_map[1]: 1st argument */
75 static const sljit_gpr r3 = 3; /* reg_map[2]: 2nd argument */
76 static const sljit_gpr r4 = 4; /* reg_map[3]: 3rd argument */
77 static const sljit_gpr r5 = 5; /* reg_map[4]: 4th argument */
78 static const sljit_gpr r6 = 6; /* reg_map[5]: 5th argument; 1st saved register */
79 static const sljit_gpr r7 = 7; /* reg_map[
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H A DsljitNativeRISCV_common.c53 static const sljit_u8 reg_map[SLJIT_NUMBER_OF_REGISTERS + 7] = { variable
65 #define RD(rd) ((sljit_ins)reg_map[rd] << 7)
66 #define RS1(rs1) ((sljit_ins)reg_map[rs1] << 15)
67 #define RS2(rs2) ((sljit_ins)reg_map[rs2] << 20)
1953 return reg_map[reg]; in sljit_get_register_index()
/third_party/mesa3d/src/etnaviv/drm-shim/
H A Detnaviv_noop.c39 const uint64_t *reg_map; member
45 .reg_map = (const uint64_t[]){
72 .reg_map = (const uint64_t[]){
99 .reg_map = (const uint64_t[]){
126 .reg_map = (const uint64_t[]){
198 gp->value = shim_gpu->reg_map[gp->param]; in etnaviv_ioctl_get_param()
/third_party/libbpf/src/
H A Dusdt.c1242 } reg_map[] = { in calc_pt_regs_off() local
1271 for (i = 0; i < ARRAY_SIZE(reg_map); i++) { in calc_pt_regs_off()
1272 for (j = 0; j < ARRAY_SIZE(reg_map[i].names); j++) { in calc_pt_regs_off()
1273 if (strcmp(reg_name, reg_map[i].names[j]) == 0) in calc_pt_regs_off()
1274 return reg_map[i].pt_regs_off; in calc_pt_regs_off()
1433 } reg_map[] = { in calc_pt_regs_off() local
1468 for (i = 0; i < ARRAY_SIZE(reg_map); i++) { in calc_pt_regs_off()
1469 if (strcmp(reg_name, reg_map[i].name) == 0) in calc_pt_regs_off()
1470 return reg_map[i].pt_regs_off; in calc_pt_regs_off()
1519 } reg_map[] in calc_pt_regs_off() local
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/third_party/mesa3d/src/compiler/nir/
H A Dnir_schedule.c132 struct hash_table *reg_map; member
246 struct hash_entry *entry = _mesa_hash_table_search(state->reg_map, in nir_schedule_reg_src_deps()
273 struct hash_entry *entry = _mesa_hash_table_search(state->reg_map, in nir_schedule_reg_dest_deps()
276 _mesa_hash_table_insert(state->reg_map, dest->reg.reg, dest_n); in nir_schedule_reg_dest_deps()
315 ralloc(state->reg_map, struct nir_schedule_class_dep); in nir_schedule_get_class_dep()
515 .reg_map = _mesa_pointer_hash_table_create(NULL), in calculate_forward_deps()
524 ralloc_free(state.reg_map); in calculate_forward_deps()
533 .reg_map = _mesa_pointer_hash_table_create(NULL), in calculate_reverse_deps()
542 ralloc_free(state.reg_map); in calculate_reverse_deps()
/third_party/mesa3d/src/broadcom/simulator/
H A Dv3dx_simulator.c249 static const uint32_t reg_map[] = { in simulator_get_param_ioctl() local
277 if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) { in simulator_get_param_ioctl()
278 args->value = V3D_READ(reg_map[args->param]); in simulator_get_param_ioctl()

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