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Searched refs:reg4 (Results 1 - 25 of 32) sorted by relevance

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/third_party/ffmpeg/libavcodec/loongarch/
H A Dvp9_idct_lsx.c376 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_lsx() local
385 reg4, reg5, reg6, reg7); in vp9_idct16_1d_columns_addblk_lsx()
413 VP9_DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vp9_idct16_1d_columns_addblk_lsx()
414 LSX_BUTTERFLY_4_H(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_lsx()
420 reg4 = __lsx_vsub_h(reg6, loc3); in vp9_idct16_1d_columns_addblk_lsx()
462 loc1 = __lsx_vadd_h(reg4, loc0); in vp9_idct16_1d_columns_addblk_lsx()
463 loc2 = __lsx_vsub_h(reg4, loc0); in vp9_idct16_1d_columns_addblk_lsx()
467 LSX_BUTTERFLY_4_H(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vp9_idct16_1d_columns_addblk_lsx()
481 DUP4_ARG2(__lsx_vsrari_h, reg0, 6, reg2, 6, reg4, in vp9_idct16_1d_columns_addblk_lsx()
502 __m128i reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; vp9_idct16_1d_columns_lsx() local
883 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
998 __m128i reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
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H A Dh264_intrapred_lasx.c30 __m256i reg0, reg1, reg2, reg3, reg4; \
75 reg4 = __lasx_xvslli_w(reg0, 3); \
76 reg4 = __lasx_xvadd_w(reg4, reg3); \
79 tmp1 = __lasx_xvadd_w(reg2, reg4); \
84 tmp3 = __lasx_xvadd_w(reg2, reg4); \
H A Dvp9_mc_lsx.c457 __m128i reg0, reg1, reg2, reg3, reg4; in common_vt_8t_4w_lsx() local
486 DUP2_ARG2(__lsx_vilvl_d, tmp1, tmp0, tmp3, tmp2, reg3, reg4); in common_vt_8t_4w_lsx()
487 DUP2_ARG2(__lsx_vxori_b, reg3, 128, reg4, 128, reg3, reg4); in common_vt_8t_4w_lsx()
490 out1 = FILT_8TAP_DPADD_S_H(reg1, reg2, reg3, reg4, filter0, filter1, in common_vt_8t_4w_lsx()
505 reg2 = reg4; in common_vt_8t_4w_lsx()
517 __m128i reg0, reg1, reg2, reg3, reg4, reg5; in common_vt_8t_8w_lsx() local
542 DUP2_ARG2(__lsx_vilvl_b, src4, src3, src6, src5, reg4, reg5); in common_vt_8t_8w_lsx()
555 out1 = FILT_8TAP_DPADD_S_H(reg3, reg4, reg5, tmp1, filter0, filter1, in common_vt_8t_8w_lsx()
559 out3 = FILT_8TAP_DPADD_S_H(reg4, reg in common_vt_8t_8w_lsx()
589 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_lsx() local
683 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_16w_mult_lsx() local
1543 __m128i reg0, reg1, reg2, reg3, reg4; common_vt_8t_and_aver_dst_4w_lsx() local
1619 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_8w_lsx() local
1705 __m128i reg0, reg1, reg2, reg3, reg4, reg5; common_vt_8t_and_aver_dst_16w_mult_lsx() local
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/third_party/vixl/src/aarch64/
H A Dregisters-aarch64.h976 const CPURegister& reg4 = NoReg,
989 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8};
1032 const CPURegister& reg4 = NoCPUReg,
1041 match &= !reg4.IsValid() || reg4.IsSameSizeAndType(reg1);
1056 const CPURegister& reg4 = NoReg,
1065 even &= !reg4.IsValid() || ((reg4.GetCode() % 2) == 0);
1081 const CPURegister& reg4 = NoCPUReg) {
1098 if (!reg4
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H A Dmacro-assembler-aarch64.cc3105 const Register& reg4) { in Emit()
3108 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3119 const VRegister& reg4) { in Emit()
3121 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3129 const CPURegister& reg4) { in Emit()
3134 const CPURegister regs[] = {reg1, reg2, reg3, reg4}; in Emit()
3169 const Register& reg4) { in Emit()
3171 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit(); in Emit()
3179 const VRegister& reg4) { in Emit()
3181 reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4 in Emit()
3102 Include(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) Emit() argument
3116 Include(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) Emit() argument
3126 Include(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) Emit() argument
3166 Exclude(const Register& reg1, const Register& reg2, const Register& reg3, const Register& reg4) Emit() argument
3176 Exclude(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) Emit() argument
3186 Exclude(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4) Emit() argument
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H A Doperands-aarch64.h45 CPURegister reg4 = NoCPUReg) in CPURegList()
46 : list_(reg1.GetBit() | reg2.GetBit() | reg3.GetBit() | reg4.GetBit()), in CPURegList()
49 VIXL_ASSERT(AreSameSizeAndType(reg1, reg2, reg3, reg4)); in CPURegList()
H A Dmacro-assembler-aarch64.h8762 const Register& reg4 = NoReg);
8766 const VRegister& reg4 = NoVReg);
8770 const CPURegister& reg4 = NoCPUReg);
8780 const Register& reg4 = NoReg);
8784 const VRegister& reg4 = NoVReg);
8788 const CPURegister& reg4 = NoCPUReg);
/third_party/node/deps/v8/src/interpreter/
H A Dbytecode-register.cc106 Register reg4, Register reg5) { in AreContiguous()
113 if (reg4.is_valid() && reg3.index() + 1 != reg4.index()) { in AreContiguous()
116 if (reg5.is_valid() && reg4.index() + 1 != reg5.index()) { in AreContiguous()
105 AreContiguous(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5) AreContiguous() argument
H A Dbytecode-register.h87 Register reg4 = invalid_value(),
/third_party/ffmpeg/libavcodec/aarch64/
H A Dvp9mc_16bpp_neon.S325 // Round, shift and saturate and store reg1-reg4
326 .macro do_store4 reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, minreg, type
330 sqrshrun \reg4\().4h, \reg4\().4s, #7
340 umin \reg4\().4h, \reg4\().4h, \minreg\().4h
345 urhadd \reg4\().4h, \reg4\().4h, \tmp4\().4h
350 st1 {\reg4\().4h}, [x0], x1
355 .macro do_store8 reg1, reg2, reg3, reg4, reg
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H A Dvp9mc_neon.S407 .macro do_store reg1, reg2, reg3, reg4, tmp1, tmp2, tmp3, tmp4, type
411 sqrshrun \reg4\().8b, \reg4\().8h, #7
420 urhadd \reg4\().8b, \reg4\().8b, \tmp4\().8b
425 st1 {\reg4\().8b}, [x0], x1
/third_party/ffmpeg/libavcodec/mips/
H A Dvp9_idct_msa.c967 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; in vp9_idct16_1d_columns_addblk_msa() local
974 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7, in vp9_idct16_1d_columns_addblk_msa()
986 VP9_DOTP_CONST_PAIR(reg4, reg12, cospi_24_64, cospi_8_64, reg4, reg12); in vp9_idct16_1d_columns_addblk_msa()
987 BUTTERFLY_4(reg8, reg0, reg4, reg12, reg2, reg6, reg10, reg14); in vp9_idct16_1d_columns_addblk_msa()
993 reg4 = reg6 - loc3; in vp9_idct16_1d_columns_addblk_msa()
1035 loc1 = reg4 + loc0; in vp9_idct16_1d_columns_addblk_msa()
1036 loc2 = reg4 - loc0; in vp9_idct16_1d_columns_addblk_msa()
1040 BUTTERFLY_4(reg8, reg10, reg11, reg5, loc0, reg4, reg9, loc1); in vp9_idct16_1d_columns_addblk_msa()
1054 SRARI_H4_SH(reg0, reg2, reg4, reg in vp9_idct16_1d_columns_addblk_msa()
1070 v8i16 reg0, reg2, reg4, reg6, reg8, reg10, reg12, reg14; vp9_idct16_1d_columns_msa() local
1634 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_even_process_store() local
1718 v8i16 reg0, reg1, reg2, reg3, reg4, reg5, reg6, reg7; vp9_idct8x32_column_odd_process_store() local
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/third_party/mesa3d/src/gallium/drivers/r600/sfn/
H A Dsfn_optimizer.cpp506 void replace_src(Instr *instr, RegisterVec4& reg4);
553 void SimplifySourceVecVisitor::replace_src(Instr *instr, RegisterVec4& reg4) in replace_src() argument
556 auto s = reg4[i]; in replace_src()
571 ReplaceConstSource visitor(instr, reg4, i); in replace_src()
/third_party/node/deps/v8/src/codegen/arm64/
H A Dregister-arm64.h515 const CPURegister& reg3 = NoReg, const CPURegister& reg4 = NoReg,
525 const CPURegister& reg3 = NoCPUReg, const CPURegister& reg4 = NoCPUReg,
534 const VRegister& reg4 = NoVReg);
543 const VRegister& reg4 = NoVReg);
H A Dassembler-arm64.cc225 const CPURegister& reg3, const CPURegister& reg4, in AreAliased()
234 const CPURegister regs[] = {reg1, reg2, reg3, reg4, reg5, reg6, reg7, reg8}; in AreAliased()
261 const CPURegister& reg3, const CPURegister& reg4, in AreSameSizeAndType()
268 match &= !reg4.is_valid() || reg4.IsSameSizeAndType(reg1); in AreSameSizeAndType()
277 const VRegister& reg3, const VRegister& reg4) { in AreSameFormat()
281 (!reg4.is_valid() || reg4.IsSameFormat(reg1)); in AreSameFormat()
285 const VRegister& reg3, const VRegister& reg4) { in AreConsecutive()
288 DCHECK(!reg3.is_valid() && !reg4 in AreConsecutive()
224 AreAliased(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) AreAliased() argument
260 AreSameSizeAndType(const CPURegister& reg1, const CPURegister& reg2, const CPURegister& reg3, const CPURegister& reg4, const CPURegister& reg5, const CPURegister& reg6, const CPURegister& reg7, const CPURegister& reg8) AreSameSizeAndType() argument
276 AreSameFormat(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) AreSameFormat() argument
284 AreConsecutive(const VRegister& reg1, const VRegister& reg2, const VRegister& reg3, const VRegister& reg4) AreConsecutive() argument
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/third_party/vixl/src/aarch32/
H A Dmacro-assembler-aarch32.cc454 CPURegister reg4) { in Printf()
462 PushRegister(reg4); in Printf()
476 uint32_t args = (reg4.GetType() << 12) | (reg3.GetType() << 8) | in Printf()
481 int size = reg4.GetRegSizeInBytes() + reg3.GetRegSizeInBytes() + in Printf()
505 if (reg4.GetType() == CPURegister::kRRegister) { in Printf()
506 available_registers.Remove(Register(reg4.GetCode())); in Printf()
516 PushRegister(reg4); in Printf()
529 PreparePrintfArgument(reg4, &core_count, &vfp_count, &printf_type); in Printf()
533 // One 32 bit argument (reg4) has been left on the stack => align the in Printf()
608 // If register reg4 wa in Printf()
450 Printf(const char* format, CPURegister reg1, CPURegister reg2, CPURegister reg3, CPURegister reg4) Printf() argument
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H A Dinstructions-aarch32.h470 constexpr RegisterList(Register reg1, Register reg2, Register reg3, Register reg4)
472 RegisterToList(reg3) | RegisterToList(reg4)) {}
561 VRegisterList(VRegister reg1, VRegister reg2, VRegister reg3, VRegister reg4)
563 RegisterToList(reg3) | RegisterToList(reg4)) {}
H A Dmacro-assembler-aarch32.h989 CPURegister reg4 = NoReg); in MacroAssembler()
13432 const Register& reg4 = NoReg) { in MacroAssembler()
13433 Include(RegisterList(reg1, reg2, reg3, reg4)); in MacroAssembler()
13439 const VRegister& reg4 = NoVReg) { in MacroAssembler()
13440 Include(VRegisterList(reg1, reg2, reg3, reg4)); in MacroAssembler()
13450 const Register& reg4 = NoReg) { in MacroAssembler()
13451 Exclude(RegisterList(reg1, reg2, reg3, reg4)); in MacroAssembler()
13457 const VRegister& reg4 = NoVReg) { in MacroAssembler()
13458 Exclude(VRegisterList(reg1, reg2, reg3, reg4)); in MacroAssembler()
/third_party/node/deps/v8/src/codegen/arm/
H A Dmacro-assembler-arm.h36 Register reg4 = no_reg,
H A Dmacro-assembler-arm.cc2616 Register reg4, Register reg5, in CallRecordWriteStub()
2618 RegList regs = {reg1, reg2, reg3, reg4, reg5, reg6}; in CallRecordWriteStub()
2615 GetRegisterThatIsNotOneOf(Register reg1, Register reg2, Register reg3, Register reg4, Register reg5, Register reg6) CallRecordWriteStub() argument
/third_party/node/deps/v8/src/codegen/loong64/
H A Dmacro-assembler-loong64.h48 Register reg4 = no_reg,
/third_party/node/deps/v8/src/codegen/mips64/
H A Dmacro-assembler-mips64.h63 Register reg4 = no_reg,
/third_party/node/deps/v8/src/codegen/mips/
H A Dmacro-assembler-mips.h53 Register reg4 = no_reg,
/third_party/node/deps/v8/src/codegen/riscv64/
H A Dmacro-assembler-riscv64.h62 Register reg4 = no_reg,
/third_party/node/deps/v8/src/codegen/ppc/
H A Dmacro-assembler-ppc.h35 Register reg4 = no_reg,

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