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Searched refs:read_domains (Results 1 - 22 of 22) sorted by relevance

/third_party/libdrm/radeon/
H A Dradeon_cs_space.c44 uint32_t read_domains, write_domain; in radeon_cs_setup_bo() local
49 read_domains = sc->read_domains; in radeon_cs_setup_bo()
54 bo->space_accounted = sc->new_accounted = (read_domains << 16) | write_domain; in radeon_cs_setup_bo()
63 if (read_domains && ((read_domains << 16) == bo->space_accounted)) { in radeon_cs_setup_bo()
77 sc->new_accounted = read_domains << 16; in radeon_cs_setup_bo()
95 } else if (read_domains & old_write) { in radeon_cs_setup_bo()
101 if (read_domains != old_read) in radeon_cs_setup_bo()
102 fprintf(stderr,"READ DOMAIN RELOC FAILURE 0x%x %d %d\n", bo->handle, read_domains, old_rea in radeon_cs_setup_bo()
166 radeon_cs_space_add_persistent_bo(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) radeon_cs_space_add_persistent_bo() argument
210 radeon_cs_space_check_with_bo(struct radeon_cs *cs, struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) radeon_cs_space_check_with_bo() argument
[all...]
H A Dradeon_cs.h98 uint32_t read_domains,
112 uint32_t read_domains,
H A Dradeon_bo_gem.c339 radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain) in radeon_gem_set_domain() argument
346 args.read_domains = read_domains; in radeon_gem_set_domain()
H A Dradeon_bo_gem.h42 int radeon_gem_set_domain(struct radeon_bo *bo, uint32_t read_domains, uint32_t write_domain);
H A Dradeon_cs_int.h7 uint32_t read_domains; member
/third_party/libdrm/intel/
H A Dintel_bufmgr.c201 uint32_t read_domains, uint32_t write_domain) in drm_intel_bo_emit_reloc()
205 read_domains, write_domain); in drm_intel_bo_emit_reloc()
212 uint32_t read_domains, uint32_t write_domain) in drm_intel_bo_emit_reloc_fence()
216 read_domains, write_domain); in drm_intel_bo_emit_reloc_fence()
199 drm_intel_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain) drm_intel_bo_emit_reloc() argument
210 drm_intel_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain) drm_intel_bo_emit_reloc_fence() argument
H A Dintel_bufmgr_priv.h181 * \param read_domains GEM read domains which the buffer will be
190 uint32_t read_domains, uint32_t write_domain);
194 uint32_t read_domains,
H A Dintel_bufmgr_fake.c83 uint32_t read_domains; member
200 uint32_t read_domains; member
1252 uint32_t read_domains, uint32_t write_domain) in drm_intel_fake_emit_reloc()
1286 r->read_domains = read_domains; in drm_intel_fake_emit_reloc()
1323 target_fake->read_domains |= r->read_domains; in drm_intel_fake_calculate_domains()
1408 bo_fake->read_domains = 0; in drm_intel_bo_fake_post_submit()
1442 batch_fake->read_domains = I915_GEM_DOMAIN_COMMAND; in drm_intel_fake_bo_exec()
1250 drm_intel_fake_emit_reloc(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain) drm_intel_fake_emit_reloc() argument
H A Dintel_bufmgr.h153 uint32_t read_domains, uint32_t write_domain);
157 uint32_t read_domains, uint32_t write_domain);
H A Dintel_bufmgr_gem.c1452 set_domain.read_domains = I915_GEM_DOMAIN_CPU; in drm_intel_gem_bo_map()
1566 set_domain.read_domains = I915_GEM_DOMAIN_GTT; in drm_intel_gem_bo_map_gtt()
1712 arg.read_domains = read; in set_domain()
1946 set_domain.read_domains = I915_GEM_DOMAIN_GTT; in drm_intel_gem_bo_start_gtt_access()
1954 set_domain.read_domains, set_domain.write_domain, in drm_intel_gem_bo_start_gtt_access()
2011 uint32_t read_domains, uint32_t write_domain, in do_bo_emit_reloc()
2077 bo_gem->relocs[bo_gem->reloc_count].read_domains = read_domains; in do_bo_emit_reloc()
2137 uint32_t read_domains, uint32_t write_domain) in drm_intel_gem_bo_emit_reloc()
2146 read_domains, write_domai in drm_intel_gem_bo_emit_reloc()
2009 do_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain, bool need_fence) do_bo_emit_reloc() argument
2135 drm_intel_gem_bo_emit_reloc(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain) drm_intel_gem_bo_emit_reloc() argument
2151 drm_intel_gem_bo_emit_reloc_fence(drm_intel_bo *bo, uint32_t offset, drm_intel_bo *target_bo, uint32_t target_offset, uint32_t read_domains, uint32_t write_domain) drm_intel_gem_bo_emit_reloc_fence() argument
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/third_party/mesa3d/src/intel/vulkan/
H A Danv_gem.c203 uint32_t read_domains, uint32_t write_domain) in anv_gem_set_domain()
207 .read_domains = read_domains, in anv_gem_set_domain()
202 anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle, uint32_t read_domains, uint32_t write_domain) anv_gem_set_domain() argument
H A Danv_gem_stubs.c129 uint32_t read_domains, uint32_t write_domain) in anv_gem_set_domain()
128 anv_gem_set_domain(struct anv_device *device, uint32_t gem_handle, uint32_t read_domains, uint32_t write_domain) anv_gem_set_domain() argument
H A Danv_batch_chain.c232 entry->read_domains = 0; in anv_reloc_list_add()
H A Danv_private.h1470 uint32_t read_domains, uint32_t write_domain);
/third_party/libdrm/nouveau/
H A Dpushbuf.c193 kref->read_domains |= domains_rd; in pushbuf_kref()
204 kref->read_domains = domains_rd; in pushbuf_kref()
281 kref->read_domains, kref->write_domains, bo->map, bo->offset, bo->size); in pushbuf_dump()
387 if (kref->read_domains) in pushbuf_submit()
768 if (kref->read_domains) in nouveau_pushbuf_refd()
/third_party/mesa3d/src/gallium/winsys/radeon/drm/
H A Dradeon_drm_cs.c311 reloc->read_domains = 0; in radeon_lookup_or_add_real_buffer()
401 added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain); in radeon_drm_cs_add_buffer()
402 reloc->read_domains |= rd; in radeon_drm_cs_add_buffer()
780 if ((usage & RADEON_USAGE_READ) && cs->csc->relocs[index].read_domains) in radeon_bo_is_referenced()
/third_party/libdrm/include/drm/
H A Dnouveau_drm.h136 __u32 read_domains; member
H A Dradeon_drm.h879 __u32 read_domains; member
979 __u32 read_domains; member
H A Di915_drm.h769 __u32 read_domains; member
813 __u32 read_domains; member
/third_party/mesa3d/include/drm-uapi/
H A Di915_drm.h1007 * Supported values for @read_domains and @write_domain:
1038 /** @read_domains: New read domains. */
1039 __u32 read_domains; member
1088 __u32 read_domains; member
/third_party/mesa3d/src/gallium/drivers/crocus/
H A Dcrocus_bufmgr.c376 .read_domains = I915_GEM_DOMAIN_CPU, in alloc_fresh_bo()
495 .read_domains = I915_GEM_DOMAIN_CPU, in crocus_bo_create_userptr()
/third_party/mesa3d/src/gallium/drivers/iris/
H A Diris_bufmgr.c1038 .read_domains = I915_GEM_DOMAIN_CPU, in alloc_fresh_bo()
1195 .read_domains = I915_GEM_DOMAIN_CPU, in iris_bo_create_userptr()

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