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Searched refs:radeon_set_config_reg (Results 1 - 15 of 15) sorted by relevance

/third_party/mesa3d/src/gallium/drivers/r600/
H A Dr600_state.c1299 radeon_set_config_reg(cs, R_008B40_PA_SC_AA_SAMPLE_LOCS_2S, sample_locs_2x[0]); in r600_emit_msaa_state()
1303 radeon_set_config_reg(cs, R_008B44_PA_SC_AA_SAMPLE_LOCS_4S, sample_locs_4x[0]); in r600_emit_msaa_state()
1660 radeon_set_config_reg(cs, R_008C04_SQ_GPR_RESOURCE_MGMT_1, a->sq_gpr_resource_mgmt_1); in r600_emit_config_state()
1661 radeon_set_config_reg(cs, R_008C08_SQ_GPR_RESOURCE_MGMT_2, a->sq_gpr_resource_mgmt_2); in r600_emit_config_state()
1897 radeon_set_config_reg(cs, R_009508_TA_CNTL_AUX, tmp); in r600_emit_seamless_cube_map()
1966 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_emit_gs_rings()
1972 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, 0); in r600_emit_gs_rings()
1977 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, in r600_emit_gs_rings()
1981 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, 0); in r600_emit_gs_rings()
1986 radeon_set_config_reg(c in r600_emit_gs_rings()
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H A Dr600_cs.h136 static inline void radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
H A Dr600_hw_context.c138 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, wait_until); in r600_flush_emit()
568 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, in r600_cp_dma_copy_buffer()
H A Dr600_state_common.c1782 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_setup_scratch_area_for_shader()
1793 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX, in r600_setup_scratch_area_for_shader()
1800 radeon_set_config_reg(cs, ring_base_reg, (rbuffer->gpu_address + size_per_se * se) >> 8); in r600_setup_scratch_area_for_shader()
1806 radeon_set_config_reg(cs, ring_size_reg, size_per_se >> 8); in r600_setup_scratch_area_for_shader()
1811 radeon_set_config_reg(cs, EG_0802C_GRBM_GFX_INDEX, in r600_setup_scratch_area_for_shader()
1818 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_setup_scratch_area_for_shader()
2403 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, in r600_draw_vbo()
2522 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in r600_draw_vbo()
H A Devergreen_compute.c634 radeon_set_config_reg(cs, R_008970_VGT_NUM_INDICES, group_size); in evergreen_emit_dispatch()
641 radeon_set_config_reg(cs, R_0089AC_VGT_COMPUTE_THREAD_GROUP_SIZE, in evergreen_emit_dispatch()
806 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (1 << 8)); in compute_emit_cs()
H A Dr600_streamout.c167 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in r600_flush_vgt_streamout()
H A Devergreen_state.c996 radeon_set_config_reg(cs, R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, (a->dyn_gpr_enabled << 8)); in evergreen_emit_config_state()
2671 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in evergreen_emit_gs_rings()
2677 radeon_set_config_reg(cs, R_008C40_SQ_ESGS_RING_BASE, in evergreen_emit_gs_rings()
2683 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, in evergreen_emit_gs_rings()
2687 radeon_set_config_reg(cs, R_008C48_SQ_GSVS_RING_BASE, in evergreen_emit_gs_rings()
2693 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, in evergreen_emit_gs_rings()
2696 radeon_set_config_reg(cs, R_008C44_SQ_ESGS_RING_SIZE, 0); in evergreen_emit_gs_rings()
2697 radeon_set_config_reg(cs, R_008C4C_SQ_GSVS_RING_SIZE, 0); in evergreen_emit_gs_rings()
2700 radeon_set_config_reg(cs, R_008040_WAIT_UNTIL, S_008040_WAIT_3D_IDLE(1)); in evergreen_emit_gs_rings()
/third_party/mesa3d/src/amd/vulkan/
H A Dradv_cs.h53 radeon_set_config_reg(struct radeon_cmdbuf *cs, unsigned reg, unsigned value) in radeon_set_config_reg() function
H A Dsi_cmd_buffer.c50 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
62 radeon_set_config_reg(cs, R_00802C_GRBM_GFX_INDEX, in si_write_harvested_raster_configs()
136 radeon_set_config_reg(cs, R_00950C_TA_CS_BC_BASE_ADDR, bc_va >> 8); in si_emit_compute()
239 radeon_set_config_reg(cs, R_008A14_PA_CL_ENHANCE, in si_emit_graphics()
H A Dradv_device.c4141 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE, S_008988_SIZE(tf_ring_size)); in radv_emit_tess_factor_ring()
4142 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE, tf_va >> 8); in radv_emit_tess_factor_ring()
4143 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM, device->physical_device->hs.hs_offchip_param); in radv_emit_tess_factor_ring()
H A Dradv_cmd_buffer.c1815 radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, d->primitive_topology); in radv_emit_primitive_topology()
10048 radeon_set_config_reg(cs, reg_strmout_cntl, 0); in radv_flush_vgt_streamout()
/third_party/mesa3d/src/gallium/drivers/radeonsi/
H A Dsi_state_streamout.c235 radeon_set_config_reg(reg_strmout_cntl, 0); in si_flush_vgt_streamout()
H A Dsi_build_pm4.h83 #define radeon_set_config_reg(reg, value) do { \ macro
H A Dsi_compute.c397 radeon_set_config_reg(R_00950C_TA_CS_BC_BASE_ADDR, sctx->border_color_buffer->gpu_address >> 8); in si_emit_initial_compute_regs()
H A Dsi_state_draw.cpp1398 radeon_set_config_reg(R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);

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