Home
last modified time | relevance | path

Searched refs:prev_inst (Results 1 - 6 of 6) sorted by relevance

/third_party/mesa3d/src/intel/compiler/
H A Dbrw_dead_control_flow.cpp52 backend_instruction *const prev_inst = prev_block->end(); in dead_control_flow_eliminate() local
58 prev_inst->opcode == BRW_OPCODE_ELSE) { in dead_control_flow_eliminate()
60 backend_instruction *const else_inst = prev_inst; in dead_control_flow_eliminate()
65 prev_inst->opcode == BRW_OPCODE_IF) { in dead_control_flow_eliminate()
69 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()
102 prev_inst->opcode == BRW_OPCODE_IF) { in dead_control_flow_eliminate()
104 backend_instruction *const if_inst = prev_inst; in dead_control_flow_eliminate()
H A Dbrw_vec4_reg_allocate.cpp279 for (vec4_instruction *prev_inst = (vec4_instruction *) inst->prev; in can_use_scratch_for_source()
280 !prev_inst->is_head_sentinel(); in can_use_scratch_for_source()
281 prev_inst = (vec4_instruction *) prev_inst->prev) { in can_use_scratch_for_source()
287 if (prev_inst->dst.file == VGRF && prev_inst->dst.nr == scratch_reg) { in can_use_scratch_for_source()
288 return (!prev_inst->predicate || prev_inst->opcode == BRW_OPCODE_SEL) && in can_use_scratch_for_source()
290 ~prev_inst->dst.writemask) == 0; in can_use_scratch_for_source()
297 if (prev_inst in can_use_scratch_for_source()
[all...]
H A Dbrw_fs.cpp3433 fs_inst *prev_inst = last_mrf_move[inst->dst.nr];
3434 if (prev_inst && prev_inst->opcode == BRW_OPCODE_MOV &&
3435 inst->dst.equals(prev_inst->dst) &&
3436 inst->src[0].equals(prev_inst->src[0]) &&
3437 inst->saturate == prev_inst->saturate &&
3438 inst->predicate == prev_inst->predicate &&
3439 inst->conditional_mod == prev_inst->conditional_mod &&
3440 inst->exec_size == prev_inst->exec_size) {
/third_party/mesa3d/src/broadcom/compiler/
H A Dqpu_schedule.c1061 struct schedule_node *prev_inst) in choose_instruction_to_schedule()
1069 if (prev_inst) { in choose_instruction_to_schedule()
1070 if (prev_inst->inst->qpu.sig.thrsw) in choose_instruction_to_schedule()
1164 if (prev_inst) { in choose_instruction_to_schedule()
1171 if (prev_inst->inst->uniform != -1 && in choose_instruction_to_schedule()
1180 if (vir_has_uniform(prev_inst->inst) && in choose_instruction_to_schedule()
1185 if ((prev_inst->inst->qpu.sig.ldunifa || in choose_instruction_to_schedule()
1186 prev_inst->inst->qpu.sig.ldunifarf) && in choose_instruction_to_schedule()
1212 &prev_inst->inst->qpu, inst)) { in choose_instruction_to_schedule()
1221 if (prev_inst) in choose_instruction_to_schedule()
1059 choose_instruction_to_schedule(struct v3d_compile *c, struct choose_scoreboard *scoreboard, struct schedule_node *prev_inst) choose_instruction_to_schedule() argument
1929 struct qinst *prev_inst = (struct qinst *) inst->link.prev; emit_branch() local
[all...]
H A Dvir.c2020 struct qinst *prev_inst = NULL; in try_opt_ldunif() local
2043 prev_inst = inst; in try_opt_ldunif()
2051 if (!prev_inst) in try_opt_ldunif()
2055 list_for_each_entry_from(struct qinst, inst, prev_inst->link.next, in try_opt_ldunif()
2057 if (inst->dst.file == prev_inst->dst.file && in try_opt_ldunif()
2058 inst->dst.index == prev_inst->dst.index) { in try_opt_ldunif()
2063 *unif = prev_inst->dst; in try_opt_ldunif()
/third_party/mesa3d/src/gallium/drivers/vc4/
H A Dvc4_qpu_schedule.c552 struct schedule_node *prev_inst) in choose_instruction_to_schedule()
560 if (prev_inst) { in choose_instruction_to_schedule()
561 uint32_t prev_sig = QPU_GET_FIELD(prev_inst->inst->inst, in choose_instruction_to_schedule()
602 if (prev_inst) { in choose_instruction_to_schedule()
611 if (prev_inst->uniform != -1 && n->uniform != -1) in choose_instruction_to_schedule()
622 inst = qpu_merge_inst(prev_inst->inst->inst, inst); in choose_instruction_to_schedule()
550 choose_instruction_to_schedule(struct choose_scoreboard *scoreboard, struct list_head *schedule_list, struct schedule_node *prev_inst) choose_instruction_to_schedule() argument

Completed in 16 milliseconds